forked from cores/microwatt
syscon: Add syscon registers
These provides some info about the SoC (though it's still somewhat incomplete and needs more work, see comments). There's also a control register for selecting DRAM vs. BRAM at 0 (and for soft-resetting the SoC but that isn't wired up yet). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>jtag-port
parent
2cef3005cd
commit
025cf5efe8
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-- syscon module, a bunch of misc global system control MMIO registers
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.wishbone_types.all;
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entity syscon is
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generic (
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SIG_VALUE : std_ulogic_vector(63 downto 0) := x"f00daa5500010001";
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CLK_FREQ : integer;
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HAS_UART : boolean;
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HAS_DRAM : boolean;
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BRAM_SIZE : integer;
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DRAM_SIZE : integer
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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-- Wishbone ports:
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wishbone_in : in wishbone_master_out;
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wishbone_out : out wishbone_slave_out;
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-- System control ports
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dram_at_0 : out std_ulogic;
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core_reset : out std_ulogic;
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soc_reset : out std_ulogic
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);
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end entity syscon;
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architecture behaviour of syscon is
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-- Register address bits
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constant SYS_REG_BITS : positive := 3;
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-- Register addresses (matches wishbone addr downto 3, ie, 8 bytes per reg)
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constant SYS_REG_SIG : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000";
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constant SYS_REG_INFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001";
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constant SYS_REG_BRAMINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "010";
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constant SYS_REG_DRAMINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "011";
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constant SYS_REG_CLKINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "100";
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constant SYS_REG_CTRL : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "101";
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-- INFO register bits
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constant SYS_REG_INFO_HAS_UART : integer := 0;
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constant SYS_REG_INFO_HAS_DRAM : integer := 1;
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-- BRAMINFO contains the BRAM size in the bottom 52 bits
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-- DRAMINFO contains the DRAM size if any in the bottom 52 bits
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-- (both have reserved top bits for future use)
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-- CLKINFO contains the CLK frequency is HZ in the bottom 40 bits
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-- CTRL register bits
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constant SYS_REG_CTRL_BITS : positive := 3;
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constant SYS_REG_CTRL_DRAM_AT_0 : integer := 0;
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constant SYS_REG_CTRL_CORE_RESET : integer := 1;
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constant SYS_REG_CTRL_SOC_RESET : integer := 2;
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-- Ctrl register
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signal reg_ctrl : std_ulogic_vector(SYS_REG_CTRL_BITS-1 downto 0);
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signal reg_ctrl_out : std_ulogic_vector(63 downto 0);
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-- Others
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signal reg_info : std_ulogic_vector(63 downto 0);
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signal reg_braminfo : std_ulogic_vector(63 downto 0);
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signal reg_draminfo : std_ulogic_vector(63 downto 0);
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signal reg_clkinfo : std_ulogic_vector(63 downto 0);
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signal info_has_dram : std_ulogic;
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signal info_has_uart : std_ulogic;
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signal info_clk : std_ulogic_vector(39 downto 0);
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begin
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-- Generated output signals
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dram_at_0 <= reg_ctrl(SYS_REG_CTRL_DRAM_AT_0);
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soc_reset <= reg_ctrl(SYS_REG_CTRL_SOC_RESET);
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core_reset <= reg_ctrl(SYS_REG_CTRL_CORE_RESET);
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-- All register accesses are single cycle
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wishbone_out.ack <= wishbone_in.cyc and wishbone_in.stb;
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wishbone_out.stall <= '0';
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-- Info register is hard wired
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info_has_uart <= '1' when HAS_UART else '0';
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info_has_dram <= '1' when HAS_DRAM else '0';
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info_clk <= std_ulogic_vector(to_unsigned(CLK_FREQ, 40));
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reg_info <= (0 => info_has_uart,
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1 => info_has_dram,
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others => '0');
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reg_braminfo <= x"000" & std_ulogic_vector(to_unsigned(BRAM_SIZE, 52));
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reg_draminfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_SIZE, 52)) when HAS_DRAM
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else (others => '0');
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reg_clkinfo <= (39 downto 0 => info_clk,
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others => '0');
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-- Control register read composition
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reg_ctrl_out <= (63 downto SYS_REG_CTRL_BITS => '0',
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SYS_REG_CTRL_BITS-1 downto 0 => reg_ctrl);
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-- Register read mux
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with wishbone_in.adr(SYS_REG_BITS+2 downto 3) select wishbone_out.dat <=
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SIG_VALUE when SYS_REG_SIG,
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reg_info when SYS_REG_INFO,
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reg_braminfo when SYS_REG_BRAMINFO,
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reg_draminfo when SYS_REG_DRAMINFO,
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reg_clkinfo when SYS_REG_CLKINFO,
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reg_ctrl_out when SYS_REG_CTRL,
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(others => '0') when others;
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-- Register writes
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regs_write: process(clk)
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begin
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if rising_edge(clk) then
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if (rst) then
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reg_ctrl <= (others => '0');
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else
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if wishbone_in.cyc and wishbone_in.stb and wishbone_in.we then
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if wishbone_in.adr(SYS_REG_BITS+2 downto 3) = SYS_REG_CTRL then
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reg_ctrl(SYS_REG_CTRL_BITS-1 downto 0) <=
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wishbone_in.dat(SYS_REG_CTRL_BITS-1 downto 0);
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end if;
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end if;
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-- Reset auto-clear
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if reg_ctrl(SYS_REG_CTRL_SOC_RESET) = '1' then
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reg_ctrl(SYS_REG_CTRL_SOC_RESET) <= '0';
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end if;
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if reg_ctrl(SYS_REG_CTRL_CORE_RESET) = '1' then
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reg_ctrl(SYS_REG_CTRL_CORE_RESET) <= '0';
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end if;
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end if;
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end if;
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end process;
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end architecture behaviour;
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