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392 lines
11 KiB
VHDL
392 lines
11 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use std.textio.all;
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use std.env.stop;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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-- Memory map:
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--
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-- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
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-- 0x40000000: DRAM (when present)
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-- 0xc0000000: SYSCON
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-- 0xc0002000: UART0
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-- 0xc0004000: XICS ICP
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-- 0xf0000000: Block RAM (aliased & repeated)
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-- 0xffff0000: DRAM init code (if any)
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entity soc is
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generic (
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MEMORY_SIZE : positive;
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RAM_INIT_FILE : string;
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RESET_LOW : boolean;
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CLK_FREQ : positive;
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SIM : boolean;
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DISABLE_FLATTEN_CORE : boolean := false;
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HAS_DRAM : boolean := false;
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DRAM_SIZE : integer := 0
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);
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port(
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rst : in std_ulogic;
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system_clk : in std_ulogic;
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-- DRAM controller signals
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wb_dram_in : out wishbone_master_out;
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wb_dram_out : in wishbone_slave_out;
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wb_dram_csr : out std_ulogic;
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wb_dram_init : out std_ulogic;
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-- UART0 signals:
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uart0_txd : out std_ulogic;
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uart0_rxd : in std_ulogic;
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-- DRAM controller signals
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alt_reset : in std_ulogic
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);
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end entity soc;
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architecture behaviour of soc is
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-- Wishbone master signals:
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signal wishbone_dcore_in : wishbone_slave_out;
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signal wishbone_dcore_out : wishbone_master_out;
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signal wishbone_icore_in : wishbone_slave_out;
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signal wishbone_icore_out : wishbone_master_out;
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signal wishbone_debug_in : wishbone_slave_out;
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signal wishbone_debug_out : wishbone_master_out;
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-- Arbiter array (ghdl doesnt' support assigning the array
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-- elements in the entity instantiation)
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constant NUM_WB_MASTERS : positive := 3;
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signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
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signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
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-- Wishbone master (output of arbiter):
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signal wb_master_in : wishbone_slave_out;
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signal wb_master_out : wishbone_master_out;
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-- Syscon signals
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signal dram_at_0 : std_ulogic;
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signal core_reset : std_ulogic;
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signal wb_syscon_in : wishbone_master_out;
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signal wb_syscon_out : wishbone_slave_out;
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-- UART0 signals:
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signal wb_uart0_in : wishbone_master_out;
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signal wb_uart0_out : wishbone_slave_out;
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signal uart_dat8 : std_ulogic_vector(7 downto 0);
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-- XICS0 signals:
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signal wb_xics0_in : wishbone_master_out;
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signal wb_xics0_out : wishbone_slave_out;
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signal int_level_in : std_ulogic_vector(15 downto 0);
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signal xics_to_execute1 : XicsToExecute1Type;
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-- Main memory signals:
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signal wb_bram_in : wishbone_master_out;
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signal wb_bram_out : wishbone_slave_out;
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constant mem_adr_bits : positive := positive(ceil(log2(real(MEMORY_SIZE))));
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-- DMI debug bus signals
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signal dmi_addr : std_ulogic_vector(7 downto 0);
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signal dmi_din : std_ulogic_vector(63 downto 0);
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signal dmi_dout : std_ulogic_vector(63 downto 0);
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signal dmi_req : std_ulogic;
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signal dmi_wr : std_ulogic;
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signal dmi_ack : std_ulogic;
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-- Per slave DMI signals
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signal dmi_wb_dout : std_ulogic_vector(63 downto 0);
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signal dmi_wb_req : std_ulogic;
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signal dmi_wb_ack : std_ulogic;
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signal dmi_core_dout : std_ulogic_vector(63 downto 0);
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signal dmi_core_req : std_ulogic;
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signal dmi_core_ack : std_ulogic;
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begin
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-- Processor core
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processor: entity work.core
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generic map(
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SIM => SIM,
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DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
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ALT_RESET_ADDRESS => (15 downto 0 => '0', others => '1')
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)
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port map(
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clk => system_clk,
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rst => rst or core_reset,
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alt_reset => alt_reset,
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wishbone_insn_in => wishbone_icore_in,
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wishbone_insn_out => wishbone_icore_out,
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wishbone_data_in => wishbone_dcore_in,
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wishbone_data_out => wishbone_dcore_out,
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dmi_addr => dmi_addr(3 downto 0),
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dmi_dout => dmi_core_dout,
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dmi_din => dmi_dout,
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dmi_wr => dmi_wr,
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dmi_ack => dmi_core_ack,
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dmi_req => dmi_core_req,
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xics_in => xics_to_execute1
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);
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-- Wishbone bus master arbiter & mux
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wb_masters_out <= (0 => wishbone_dcore_out,
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1 => wishbone_icore_out,
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2 => wishbone_debug_out);
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wishbone_dcore_in <= wb_masters_in(0);
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wishbone_icore_in <= wb_masters_in(1);
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wishbone_debug_in <= wb_masters_in(2);
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wishbone_arbiter_0: entity work.wishbone_arbiter
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generic map(
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NUM_MASTERS => NUM_WB_MASTERS
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)
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port map(
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clk => system_clk, rst => rst,
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wb_masters_in => wb_masters_out,
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wb_masters_out => wb_masters_in,
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wb_slave_out => wb_master_out,
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wb_slave_in => wb_master_in
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);
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-- Wishbone slaves address decoder & mux
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slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out, wb_dram_out, wb_syscon_out)
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-- Selected slave
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type slave_type is (SLAVE_SYSCON,
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SLAVE_UART,
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SLAVE_BRAM,
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SLAVE_DRAM,
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SLAVE_DRAM_INIT,
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SLAVE_DRAM_CSR,
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SLAVE_ICP_0,
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SLAVE_NONE);
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variable slave : slave_type;
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begin
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-- Simple address decoder.
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slave := SLAVE_NONE;
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-- Simple address decoder. Ignore top bits to save silicon for now
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slave := SLAVE_NONE;
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if std_match(wb_master_out.adr, x"0-------") then
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slave := SLAVE_DRAM when HAS_DRAM and dram_at_0 = '1' else
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SLAVE_BRAM;
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elsif std_match(wb_master_out.adr, x"FFFF----") then
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slave := SLAVE_DRAM_INIT;
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elsif std_match(wb_master_out.adr, x"F-------") then
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slave := SLAVE_BRAM;
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elsif std_match(wb_master_out.adr, x"4-------") and HAS_DRAM then
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slave := SLAVE_DRAM;
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elsif std_match(wb_master_out.adr, x"C0000---") then
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slave := SLAVE_SYSCON;
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elsif std_match(wb_master_out.adr, x"C0002---") then
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slave := SLAVE_UART;
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elsif std_match(wb_master_out.adr, x"C01-----") then
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slave := SLAVE_DRAM_CSR;
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elsif std_match(wb_master_out.adr, x"C0004---") then
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slave := SLAVE_ICP_0;
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end if;
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-- Wishbone muxing. Defaults:
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wb_bram_in <= wb_master_out;
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wb_bram_in.cyc <= '0';
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wb_uart0_in <= wb_master_out;
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wb_uart0_in.cyc <= '0';
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-- Only give xics 8 bits of wb addr
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wb_xics0_in <= wb_master_out;
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wb_xics0_in.adr <= (others => '0');
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wb_xics0_in.adr(7 downto 0) <= wb_master_out.adr(7 downto 0);
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wb_xics0_in.cyc <= '0';
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wb_dram_in <= wb_master_out;
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wb_dram_in.cyc <= '0';
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wb_dram_csr <= '0';
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wb_dram_init <= '0';
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wb_syscon_in <= wb_master_out;
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wb_syscon_in.cyc <= '0';
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case slave is
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when SLAVE_BRAM =>
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wb_bram_in.cyc <= wb_master_out.cyc;
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wb_master_in <= wb_bram_out;
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when SLAVE_DRAM =>
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wb_dram_in.cyc <= wb_master_out.cyc;
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wb_master_in <= wb_dram_out;
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when SLAVE_DRAM_INIT =>
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wb_dram_in.cyc <= wb_master_out.cyc;
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wb_master_in <= wb_dram_out;
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wb_dram_init <= '1';
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when SLAVE_DRAM_CSR =>
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wb_dram_in.cyc <= wb_master_out.cyc;
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wb_master_in <= wb_dram_out;
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wb_dram_csr <= '1';
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when SLAVE_SYSCON =>
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wb_syscon_in.cyc <= wb_master_out.cyc;
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wb_master_in <= wb_syscon_out;
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when SLAVE_UART =>
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wb_uart0_in.cyc <= wb_master_out.cyc;
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wb_master_in <= wb_uart0_out;
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when SLAVE_ICP_0 =>
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wb_xics0_in.cyc <= wb_master_out.cyc;
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wb_master_in <= wb_xics0_out;
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when others =>
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wb_master_in.dat <= (others => '1');
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wb_master_in.ack <= wb_master_out.stb and wb_master_out.cyc;
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wb_master_in.stall <= '0';
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end case;
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end process slave_intercon;
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-- Syscon slave
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syscon0: entity work.syscon
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generic map(
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HAS_UART => true,
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HAS_DRAM => HAS_DRAM,
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BRAM_SIZE => MEMORY_SIZE,
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DRAM_SIZE => DRAM_SIZE,
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CLK_FREQ => CLK_FREQ
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)
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port map(
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clk => system_clk,
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rst => rst,
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wishbone_in => wb_syscon_in,
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wishbone_out => wb_syscon_out,
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dram_at_0 => dram_at_0,
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core_reset => core_reset,
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soc_reset => open -- XXX TODO
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);
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-- Simulated memory and UART
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-- UART0 wishbone slave
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-- XXX FIXME: Need a proper wb64->wb8 adapter that
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-- converts SELs into low address bits and muxes
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-- data accordingly (either that or rejects large
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-- cycles).
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uart0: entity work.pp_soc_uart
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generic map(
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FIFO_DEPTH => 32
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)
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port map(
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clk => system_clk,
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reset => rst,
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txd => uart0_txd,
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rxd => uart0_rxd,
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irq => int_level_in(0),
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wb_adr_in => wb_uart0_in.adr(11 downto 0),
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wb_dat_in => wb_uart0_in.dat(7 downto 0),
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wb_dat_out => uart_dat8,
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wb_cyc_in => wb_uart0_in.cyc,
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wb_stb_in => wb_uart0_in.stb,
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wb_we_in => wb_uart0_in.we,
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wb_ack_out => wb_uart0_out.ack
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);
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wb_uart0_out.dat <= x"00000000000000" & uart_dat8;
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wb_uart0_out.stall <= '0' when wb_uart0_in.cyc = '0' else not wb_uart0_out.ack;
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xics0: entity work.xics
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generic map(
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LEVEL_NUM => 16
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)
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port map(
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clk => system_clk,
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rst => rst,
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wb_in => wb_xics0_in,
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wb_out => wb_xics0_out,
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int_level_in => int_level_in,
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e_out => xics_to_execute1
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);
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-- BRAM Memory slave
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bram0: entity work.wishbone_bram_wrapper
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generic map(
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MEMORY_SIZE => MEMORY_SIZE,
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RAM_INIT_FILE => RAM_INIT_FILE
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)
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port map(
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clk => system_clk,
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rst => rst,
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wishbone_in => wb_bram_in,
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wishbone_out => wb_bram_out
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);
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-- DMI(debug bus) <-> JTAG bridge
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dtm: entity work.dmi_dtm
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generic map(
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ABITS => 8,
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DBITS => 64
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)
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port map(
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sys_clk => system_clk,
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sys_reset => rst,
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dmi_addr => dmi_addr,
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dmi_din => dmi_din,
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dmi_dout => dmi_dout,
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dmi_req => dmi_req,
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dmi_wr => dmi_wr,
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dmi_ack => dmi_ack
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);
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-- DMI interconnect
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dmi_intercon: process(dmi_addr, dmi_req,
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dmi_wb_ack, dmi_wb_dout,
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dmi_core_ack, dmi_core_dout)
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-- DMI address map (each address is a full 64-bit register)
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--
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-- Offset: Size: Slave:
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-- 0 4 Wishbone
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-- 10 16 Core
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type slave_type is (SLAVE_WB,
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SLAVE_CORE,
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SLAVE_NONE);
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variable slave : slave_type;
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begin
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-- Simple address decoder
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slave := SLAVE_NONE;
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if std_match(dmi_addr, "000000--") then
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slave := SLAVE_WB;
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elsif std_match(dmi_addr, "0001----") then
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slave := SLAVE_CORE;
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end if;
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-- DMI muxing
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dmi_wb_req <= '0';
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dmi_core_req <= '0';
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case slave is
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when SLAVE_WB =>
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dmi_wb_req <= dmi_req;
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dmi_ack <= dmi_wb_ack;
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dmi_din <= dmi_wb_dout;
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when SLAVE_CORE =>
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dmi_core_req <= dmi_req;
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dmi_ack <= dmi_core_ack;
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dmi_din <= dmi_core_dout;
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when others =>
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dmi_ack <= dmi_req;
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dmi_din <= (others => '1');
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end case;
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-- SIM magic exit
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if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
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stop;
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end if;
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end process;
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-- Wishbone debug master (TODO: Add a DMI address decoder)
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wishbone_debug: entity work.wishbone_debug_master
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port map(clk => system_clk, rst => rst,
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dmi_addr => dmi_addr(1 downto 0),
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dmi_dout => dmi_wb_dout,
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dmi_din => dmi_dout,
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dmi_wr => dmi_wr,
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dmi_ack => dmi_wb_ack,
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dmi_req => dmi_wb_req,
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wb_in => wishbone_debug_in,
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wb_out => wishbone_debug_out);
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end architecture behaviour;
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