doc: Update README.md to link to Intel LPC spec

Signed-off-by: Michael Neuling <mikey@neuling.org>
master
Michael Neuling 3 years ago
parent 0d4c7bd55a
commit 144580736a

@ -4,6 +4,9 @@ This is an LPC peripheral that implements LPC IO and FW cycles so that
it can boot a host like a POWER9. This peripheral would typically sit
inside a BMC SoC.

It implements the Intel Low Pin Count (LPC) spec from
[here](https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf).

# System diagram
```
.

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