An experimental small core based on VexRiscv, written in Scala

Updated 2 years ago

Fork LibreBMC from page to edit the text.

Updated 2 years ago

This is the main libreBMC repo that contains an overview of the project and useful links. Start here.

Updated 2 years ago

This is the main libreBMC repo that contains an overview of the project and useful links. Start here.

Updated 2 years ago

A set of testing utilities for testing SMT performance on POWER9 bare metal and a set of guest VMs set to test the host.

Updated 1 year ago

A collection of scripts and meta data for managing the OPF Hub systems with IPMI via the OpenBMC.

Updated 1 year ago

Updated 1 year ago

The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue

Updated 1 year ago

Updated 11 months ago

High-specific-bandwidth memory design

Updated 9 months ago

Updated 2 weeks ago

A tiny Open POWER ISA softcore written in VHDL 2008

Updated 6 days ago

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Updated 6 hours ago