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openpowerwtf 37c11cc2bd add custom 2 years ago
build init 2 years ago
sim init 2 years ago
src add custom 2 years ago init 2 years ago

Logical Array Wrapper

  • verilog is in rtl/src/array
  • parameter determines sim vs tech during rtl compile

Physical Array

  • custom cell(s) to be designed
  • custom/

Test Site

  • verilog is in rtl/src/site
  • supporting logic for test and debug through available Caravel connections


  • rtl/sim/coco