add custom

master
openpowerwtf 2 years ago
parent f9d5f06f61
commit 37c11cc2bd

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

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* NGSPICE file created from 10T_1x8_magic.ext - technology: sky130A

.subckt x10T_toy_magic WWL RWL WBL WBLb RBL0 RBL1 VDD GND
X0 junc0 junc1 VDD VDD sky130_fd_pr__pfet_01v8 ad=1.29e+10p pd=430000u as=6.26e+10p ps=1.44e+06u w=1 l=0.15
X1 GND junc0 junc1 GND sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=4.8725e+10p ps=1.28e+06u w=1 l=0.15
X2 RWL0_junc junc0 GND GND sky130_fd_pr__nfet_01v8 ad=4.795e+10p pd=980000u as=2.252e+11p ps=4.64e+06u w=1 l=0.15
X3 VDD junc0 junc1 VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=1.68e+10p ps=520000u w=1 l=0.15
X4 WBL WWL junc0 GND sky130_fd_pr__nfet_01v8 ad=2.4175e+10p pd=630000u as=4.935e+10p ps=1.28e+06u w=1 l=0.15
X5 junc1 WWL WBLb GND sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.31e+10p ps=610000u w=1 l=0.15
X6 GND junc1 RWL1_junc GND sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=4.795e+10p ps=980000u w=1 l=0.15
X7 RBL0 RWL RWL0_junc GND sky130_fd_pr__nfet_01v8 ad=4.515e+10p pd=850000u as=0p ps=0u w=1 l=0.15
X8 junc0 junc1 GND GND sky130_fd_pr__nfet_01v8 ad=2.4225e+11p pd=3.81e+06u as=0p ps=0u w=1 l=0.15
X9 RWL1_junc RWL RBL1 GND sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=4.515e+10p ps=850000u w=1 l=0.15
.ends

.subckt x10T_1x8_magic WWL RWL WBLb_0 WBL_0 RBL1_0 RBL0_0 WBLb_1 WBL_1 RBL1_1 RBL0_1
+ WBLb_2 WBL_2 RBL1_2 RBL0_2 WBLb_3 WBL_3 RBL1_3 RBL0_3 WBLb_4 WBL_4 RBL1_4 RBL0_4
+ WBLb_5 WBL_5 RBL1_5 RBL0_5 WBLb_6 WBL_6 RBL1_6 RBL0_6 WBLb_7 WBL_7 RBL1_7 RBL0_7
+ VDD GND
X10T_toy_magic_0 WWL RWL WBL_0 WBLb_0 RBL0_0 RBL1_0 VDD GND x10T_toy_magic
X10T_toy_magic_1 WWL RWL WBL_1 WBLb_1 RBL0_1 RBL1_1 VDD GND x10T_toy_magic
X10T_toy_magic_2 WWL RWL WBL_2 WBLb_2 RBL0_2 RBL1_2 VDD GND x10T_toy_magic
X10T_toy_magic_3 WWL RWL WBL_3 WBLb_3 RBL0_3 RBL1_3 VDD GND x10T_toy_magic
X10T_toy_magic_4 WWL RWL WBL_4 WBLb_4 RBL0_4 RBL1_4 VDD GND x10T_toy_magic
X10T_toy_magic_5 WWL RWL WBL_5 WBLb_5 RBL0_5 RBL1_5 VDD GND x10T_toy_magic
X10T_toy_magic_6 WWL RWL WBL_6 WBLb_6 RBL0_6 RBL1_6 VDD GND x10T_toy_magic
X10T_toy_magic_7 WWL RWL WBL_7 WBLb_7 RBL0_7 RBL1_7 VDD GND x10T_toy_magic
.ends

@ -0,0 +1,58 @@
Flattening unmatched subcell INVX1 in circuit 10T_toy_xschem (1)(2 instances)
Flattening unmatched subcell x10T_toy_magic in circuit x10T_1x8_magic (0)(8 instances)
Flattening unmatched subcell 10T_toy_xschem in circuit 10T_1x8_xschem (1)(8 instances)

Subcircuit summary:
Circuit 1: x10T_1x8_magic |Circuit 2: 10T_1x8_xschem
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8 (16) |sky130_fd_pr__pfet_01v8 (16)
sky130_fd_pr__nfet_01v8 (64) |sky130_fd_pr__nfet_01v8 (64)
Number of devices: 80 |Number of devices: 80
Number of nets: 68 |Number of nets: 68
---------------------------------------------------------------------------------------
Netlists match uniquely.
Circuits match correctly.

Subcircuit pins:
Circuit 1: x10T_1x8_magic |Circuit 2: 10T_1x8_xschem
-------------------------------------------|-------------------------------------------
GND |GND
VDD |VDD
RBL1_7 |RBL1_7
RBL0_7 |RBL0_7
RBL1_6 |RBL1_6
RBL0_6 |RBL0_6
RBL1_5 |RBL1_5
RBL0_5 |RBL0_5
RBL1_4 |RBL1_4
RBL0_4 |RBL0_4
RBL1_3 |RBL1_3
RBL0_3 |RBL0_3
RBL1_2 |RBL1_2
RBL0_2 |RBL0_2
RBL1_1 |RBL1_1
RBL0_1 |RBL0_1
RBL1_0 |RBL1_0
RBL0_0 |RBL0_0
WBLb_7 |WBLb_7
WBL_7 |WBL_7
WBLb_6 |WBLb_6
WBL_6 |WBL_6
WBLb_5 |WBLb_5
WBL_5 |WBL_5
WBLb_4 |WBLb_4
WBL_4 |WBL_4
WBLb_3 |WBLb_3
WBL_3 |WBL_3
WBLb_2 |WBLb_2
WBL_2 |WBL_2
WBLb_1 |WBLb_1
WBL_1 |WBL_1
WBLb_0 |WBLb_0
WBL_0 |WBL_0
WWL |WWL
RWL |RWL
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes x10T_1x8_magic and 10T_1x8_xschem are equivalent.
Circuits match uniquely.

File diff suppressed because it is too large Load Diff

@ -0,0 +1,91 @@
* NGSPICE file created from 10T_1x8_magic_flattened.ext - technology: sky130A

.subckt x10T_1x8_magic_flattened
+ WWL RWL
+ WBLb_0 WBL_0 WBLb_1 WBL_1 WBLb_2 WBL_2 WBLb_3 WBL_3 WBLb_4 WBL_4 WBLb_5 WBL_5 WBLb_6 WBL_6 WBLb_7 WBL_7
+ RBL0_0 RBL0_1 RBL0_2 RBL0_3 RBL0_4 RBL0_5 RBL0_6 RBL0_7
+ RBL1_0 RBL1_1 RBL1_2 RBL1_3 RBL1_4 RBL1_5 RBL1_6 RBL1_7
+ VDD GND

M1000 10T_toy_magic_0/junc0 10T_toy_magic_0/junc1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
M1001 10T_toy_magic_6/RWL1_junc RWL RBL1_1 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1002 10T_toy_magic_5/RWL1_junc RWL RBL1_2 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1003 10T_toy_magic_0/RWL1_junc RWL RBL1_6 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1004 VDD 10T_toy_magic_5/junc0 10T_toy_magic_5/junc1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
M1005 WBL_2 WWL 10T_toy_magic_5/junc0 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1006 10T_toy_magic_6/junc0 10T_toy_magic_6/junc1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
M1007 10T_toy_magic_3/junc0 10T_toy_magic_3/junc1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
M1008 10T_toy_magic_7/RWL0_junc 10T_toy_magic_7/junc0 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1009 10T_toy_magic_4/junc0 10T_toy_magic_4/junc1 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1010 10T_toy_magic_2/RWL0_junc 10T_toy_magic_2/junc0 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1011 10T_toy_magic_1/junc0 10T_toy_magic_1/junc1 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1012 GND 10T_toy_magic_7/junc0 10T_toy_magic_7/junc1 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1013 GND 10T_toy_magic_2/junc0 10T_toy_magic_2/junc1 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1014 10T_toy_magic_1/junc1 WWL WBLb_7 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1015 10T_toy_magic_7/RWL1_junc RWL RBL1_0 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1016 GND 10T_toy_magic_7/junc1 10T_toy_magic_7/RWL1_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1017 10T_toy_magic_4/RWL1_junc RWL RBL1_3 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1018 GND 10T_toy_magic_2/junc1 10T_toy_magic_2/RWL1_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1019 WBL_6 WWL 10T_toy_magic_0/junc0 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1020 RBL0_0 RWL 10T_toy_magic_7/RWL0_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1021 RBL0_1 RWL 10T_toy_magic_6/RWL0_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1022 10T_toy_magic_3/junc0 10T_toy_magic_3/junc1 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1023 RBL0_5 RWL 10T_toy_magic_2/RWL0_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1024 10T_toy_magic_0/RWL0_junc 10T_toy_magic_0/junc0 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1025 VDD 10T_toy_magic_3/junc0 10T_toy_magic_3/junc1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
M1026 10T_toy_magic_2/junc1 WWL WBLb_5 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1027 GND 10T_toy_magic_6/junc0 10T_toy_magic_6/junc1 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1028 10T_toy_magic_6/RWL0_junc 10T_toy_magic_6/junc0 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1029 10T_toy_magic_5/RWL0_junc 10T_toy_magic_5/junc0 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1030 GND 10T_toy_magic_0/junc0 10T_toy_magic_0/junc1 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1031 WBL_4 WWL 10T_toy_magic_3/junc0 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1032 GND 10T_toy_magic_6/junc1 10T_toy_magic_6/RWL1_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1033 GND 10T_toy_magic_0/junc1 10T_toy_magic_0/RWL1_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1034 WBL_1 WWL 10T_toy_magic_6/junc0 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1035 GND 10T_toy_magic_5/junc0 10T_toy_magic_5/junc1 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1036 RBL0_6 RWL 10T_toy_magic_0/RWL0_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1037 10T_toy_magic_7/junc1 WWL WBLb_0 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1038 10T_toy_magic_4/junc1 WWL WBLb_3 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1039 GND 10T_toy_magic_5/junc1 10T_toy_magic_5/RWL1_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1040 RBL0_2 RWL 10T_toy_magic_5/RWL0_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1041 10T_toy_magic_4/junc0 10T_toy_magic_4/junc1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
M1042 GND 10T_toy_magic_4/junc0 10T_toy_magic_4/junc1 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1043 10T_toy_magic_1/RWL1_junc RWL RBL1_7 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1044 VDD 10T_toy_magic_0/junc0 10T_toy_magic_0/junc1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
M1045 GND 10T_toy_magic_4/junc1 10T_toy_magic_4/RWL1_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1046 10T_toy_magic_1/junc0 10T_toy_magic_1/junc1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
M1047 VDD 10T_toy_magic_6/junc0 10T_toy_magic_6/junc1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
M1048 WBL_3 WWL 10T_toy_magic_4/junc0 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1049 10T_toy_magic_3/RWL1_junc RWL RBL1_4 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1050 10T_toy_magic_2/junc0 10T_toy_magic_2/junc1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
M1051 10T_toy_magic_7/junc0 10T_toy_magic_7/junc1 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1052 10T_toy_magic_2/junc0 10T_toy_magic_2/junc1 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1053 10T_toy_magic_1/RWL0_junc 10T_toy_magic_1/junc0 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1054 10T_toy_magic_5/junc1 WWL WBLb_2 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1055 10T_toy_magic_4/RWL0_junc 10T_toy_magic_4/junc0 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1056 VDD 10T_toy_magic_1/junc0 10T_toy_magic_1/junc1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
M1057 10T_toy_magic_2/RWL1_junc RWL RBL1_5 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1058 GND 10T_toy_magic_1/junc0 10T_toy_magic_1/junc1 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1059 10T_toy_magic_7/junc0 10T_toy_magic_7/junc1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
M1060 WBL_7 WWL 10T_toy_magic_1/junc0 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1061 RBL0_3 RWL 10T_toy_magic_4/RWL0_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1062 GND 10T_toy_magic_1/junc1 10T_toy_magic_1/RWL1_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1063 RBL0_7 RWL 10T_toy_magic_1/RWL0_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1064 VDD 10T_toy_magic_2/junc0 10T_toy_magic_2/junc1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
M1065 10T_toy_magic_0/junc1 WWL WBLb_6 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1066 10T_toy_magic_3/RWL0_junc 10T_toy_magic_3/junc0 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1067 WBL_5 WWL 10T_toy_magic_2/junc0 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1068 10T_toy_magic_6/junc0 10T_toy_magic_6/junc1 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1069 10T_toy_magic_5/junc0 10T_toy_magic_5/junc1 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1070 10T_toy_magic_0/junc0 10T_toy_magic_0/junc1 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1071 VDD 10T_toy_magic_4/junc0 10T_toy_magic_4/junc1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
M1072 10T_toy_magic_3/junc1 WWL WBLb_4 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1073 GND 10T_toy_magic_3/junc0 10T_toy_magic_3/junc1 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1074 VDD 10T_toy_magic_7/junc0 10T_toy_magic_7/junc1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
M1075 10T_toy_magic_6/junc1 WWL WBLb_1 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1076 GND 10T_toy_magic_3/junc1 10T_toy_magic_3/RWL1_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1077 WBL_0 WWL 10T_toy_magic_7/junc0 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1078 RBL0_4 RWL 10T_toy_magic_3/RWL0_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
M1079 10T_toy_magic_5/junc0 10T_toy_magic_5/junc1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
.ends

@ -0,0 +1,45 @@
** sch_path: /home/rjridle/osu-toy-sram/xschem/10T_1x8_xschem.sch

.subckt 10T_1x8_xschem
+ WWL RWL
+ WBLb_0 WBL_0 WBLb_1 WBL_1 WBLb_2 WBL_2 WBLb_3 WBL_3 WBLb_4 WBL_4 WBLb_5 WBL_5 WBLb_6 WBL_6 WBLb_7 WBL_7
+ RBL0_0 RBL0_1 RBL0_2 RBL0_3 RBL0_4 RBL0_5 RBL0_6 RBL0_7
+ RBL1_0 RBL1_1 RBL1_2 RBL1_3 RBL1_4 RBL1_5 RBL1_6 RBL1_7
+ VDD GND

x1 WWL WBL_0 RBL0_0 RBL1_0 WBLb_0 RWL RWL VDD GND 10T_toy_xschem
x2 WWL WBL_1 RBL0_1 RBL1_1 WBLb_1 RWL RWL VDD GND 10T_toy_xschem
x3 WWL WBL_2 RBL0_2 RBL1_2 WBLb_2 RWL RWL VDD GND 10T_toy_xschem
x4 WWL WBL_3 RBL0_3 RBL1_3 WBLb_3 RWL RWL VDD GND 10T_toy_xschem
x5 WWL WBL_4 RBL0_4 RBL1_4 WBLb_4 RWL RWL VDD GND 10T_toy_xschem
x6 WWL WBL_5 RBL0_5 RBL1_5 WBLb_5 RWL RWL VDD GND 10T_toy_xschem
x7 WWL WBL_6 RBL0_6 RBL1_6 WBLb_6 RWL RWL VDD GND 10T_toy_xschem
x8 WWL WBL_7 RBL0_7 RBL1_7 WBLb_7 RWL RWL VDD GND 10T_toy_xschem
.ends

* expanding symbol: 10T_toy_xschem.sym # of pins=7
** sym_path: /home/rjridle/osu-toy-sram/xschem/10T_toy_xschem.sym
** sch_path: /home/rjridle/osu-toy-sram/xschem/10T_toy_xschem.sch
.subckt 10T_toy_xschem WWL WBL RBL0 RBL1 WBLb RWL0 RWL1 VDD GND
*.PININFO WWL:I RWL0:I RWL1:I WBL:I WBLb:I RBL0:O RBL1:O
x1 net1 net2 VDD GND INVX1
x2 net2 net1 VDD GND INVX1
XM1 net2 WWL WBL GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM2 WBLb WWL net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM3 net3 net2 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM4 RBL0 RWL0 net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM5 net4 net1 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM6 RBL1 RWL1 net4 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
.ends


* expanding symbol: INVX1.sym # of pins=2
** sym_path: /home/rjridle/osu-toy-sram/xschem/INVX1.sym
** sch_path: /home/rjridle/osu-toy-sram/xschem/INVX1.sch
.subckt INVX1 Y A VDD GND
*.PININFO A:I Y:O
XM1 Y A GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM2 Y A VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1
.ends

.end

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

@ -0,0 +1,426 @@
** sch_path: /home/rjridle/osu-toy-sram/xschem/10T_32x32_xschem.sch
.subckt 10T_32x32_xschem WWL_0 RWL_0 WWL_1 RWL_1 WWL_2 RWL_2 WWL_3 RWL_3 WWL_4 RWL_4 WWL_5 RWL_5
+ WWL_6 RWL_6 WWL_7 RWL_7 WWL_8 RWL_8 WWL_9 RWL_9 WWL_10 RWL_10 WWL_11 RWL_11 WWL_12 RWL_12 WWL_13 RWL_13
+ WWL_14 RWL_14 WWL_15 RWL_15 WWL_16 RWL_16 WWL_17 RWL_17 WWL_18 RWL_18 WWL_19 RWL_19 WWL_20 RWL_20 WWL_21
+ RWL_21 WWL_22 RWL_22 WWL_23 RWL_23 WWL_24 RWL_24 WWL_25 RWL_25 WWL_26 RWL_26 WWL_27 RWL_27 WWL_28 RWL_28
+ WWL_29 RWL_29 WWL_30 RWL_30 WWL_31 RWL_31 RBL1_0 RBL0_0 RBL1_1 RBL0_1 RBL1_2 RBL0_2 RBL0_3 RBL1_3 RBL0_4
+ RBL1_4 RBL0_5 RBL1_5 RBL0_6 RBL1_6 RBL0_7 RBL1_7 RBL0_8 RBL1_8 RBL0_9 RBL1_9 RBL0_10 RBL1_10 RBL0_11
+ RBL1_11 RBL0_12 RBL1_12 RBL0_13 RBL1_13 RBL0_14 RBL1_14 RBL0_15 RBL1_15 RBL0_16 RBL1_16 RBL0_17 RBL1_17
+ RBL0_18 RBL1_18 RBL0_19 RBL1_19 RBL0_20 RBL1_20 RBL0_21 RBL0_22 RBL0_23 RBL1_21 RBL1_22 RBL1_23 RBL0_24
+ RBL1_24 RBL0_25 RBL1_25 RBL0_26 RBL1_26 RBL0_27 RBL1_27 RBL0_28 RBL1_28 RBL0_29 RBL1_29 RBL0_30 RBL1_30
+ RBL0_31 RBL1_31 WBL_0 WBLb_0 WBL_1 WBLb_1 WBL_2 WBLb_2 WBL_3 WBLb_3 WBL_4 WBLb_4 WBL_5 WBLb_5 WBL_6 WBLb_6
+ WBL_7 WBLb_7 WBL_8 WBLb_8 WBL_9 WBLb_9 WBL_10 WBLb_10 WBL_11 WBLb_11 WBL_12 WBLb_12 WBL_13 WBLb_13 WBL_14
+ WBLb_14 WBL_15 WBLb_15 WBL_16 WBLb_16 WBL_17 WBLb_17 WBL_18 WBLb_18 WBL_19 WBLb_19 WBL_20 WBLb_20 WBL_21
+ WBLb_21 WBL_22 WBLb_22 WBL_23 WBLb_23 WBL_24 WBLb_24 WBL_25 WBLb_25 WBLb_26 WBL_26 WBL_27 WBLb_27 WBL_28
+ WBLb_28 WBL_29 WBLb_29 WBL_30 WBLb_30 WBL_31 WBLb_31 VDD GND

x1 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_2 RWL_2 VDD GND 10T_1x32_xschem
x2 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_3 RWL_3 VDD GND 10T_1x32_xschem
x3 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_4 RWL_4 VDD GND 10T_1x32_xschem
x4 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_5 RWL_5 VDD GND 10T_1x32_xschem
x5 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_6 RWL_6 VDD GND 10T_1x32_xschem
x6 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_7 RWL_7 VDD GND 10T_1x32_xschem
x7 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_1 RWL_1 VDD GND 10T_1x32_xschem
x8 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_0 RWL_0 VDD GND 10T_1x32_xschem
x9 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_8 RWL_8 VDD GND 10T_1x32_xschem
x10 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_9 RWL_9 VDD GND 10T_1x32_xschem
x11 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_12 RWL_12 VDD GND 10T_1x32_xschem
x12 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_13 RWL_13 VDD GND 10T_1x32_xschem
x13 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_14 RWL_14 VDD GND 10T_1x32_xschem
x14 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_15 RWL_15 VDD GND 10T_1x32_xschem
x15 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_16 RWL_16 VDD GND 10T_1x32_xschem
x16 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_17 RWL_17 VDD GND 10T_1x32_xschem
x17 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_11 RWL_11 VDD GND 10T_1x32_xschem
x18 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_10 RWL_10 VDD GND 10T_1x32_xschem
x19 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_18 RWL_18 VDD GND 10T_1x32_xschem
x20 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_19 RWL_19 VDD GND 10T_1x32_xschem
x21 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_22 RWL_22 VDD GND 10T_1x32_xschem
x22 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_23 RWL_23 VDD GND 10T_1x32_xschem
x23 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_24 RWL_24 VDD GND 10T_1x32_xschem
x24 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_25 RWL_25 VDD GND 10T_1x32_xschem
x25 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_26 RWL_26 VDD GND 10T_1x32_xschem
x26 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_27 RWL_27 VDD GND 10T_1x32_xschem
x27 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_21 RWL_21 VDD GND 10T_1x32_xschem
x28 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_20 RWL_20 VDD GND 10T_1x32_xschem
x29 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_28 RWL_28 VDD GND 10T_1x32_xschem
x30 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_29 RWL_29 VDD GND 10T_1x32_xschem
x31 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_30 RWL_30 VDD GND 10T_1x32_xschem
x32 RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18 RBL0_26 WBL_26 WBL_2
+ RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11 WBLb_30 WBLb_22 RBL0_31
+ RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13 RBL1_5 WBL_4 RBL1_20
+ WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27 RBL1_3 WBLb_5 WBLb_13
+ RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29 WBLb_18 RBL0_21 WBLb_10
+ RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9 WBLb_24 WBLb_16 RBL1_23
+ RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1 WBL_13 RBL0_9 RBL0_28
+ WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19 WBL_14 RBL0_11 WBL_6
+ RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31 WBLb_23 RBL0_16 RBL0_8
+ WBLb_15 RBL0_0 WBLb_7 WWL_31 RWL_31 VDD GND 10T_1x32_xschem
.ends

.subckt 10T_1x32_xschem RBL0_22 WBL_25 RBL0_30 WBL_17 WBL_9 WBL_1 RBL0_14 RBL0_6 WBL_18 RBL0_18
+ RBL0_26 WBL_26 WBL_2 RBL0_2 RBL0_10 WBL_10 WBL_19 WBL_27 RBL1_30 RBL1_22 RBL1_14 WBL_3 RBL1_6 WBL_11
+ WBLb_30 WBLb_22 RBL0_31 RBL0_23 RBL0_7 RBL0_15 WBLb_6 WBLb_14 RBL1_21 WBL_20 RBL1_29 WBL_28 WBL_12 RBL1_13
+ RBL1_5 WBL_4 RBL1_20 WBL_23 WBL_31 RBL1_28 WBL_15 RBL1_4 RBL1_12 WBL_7 WBLb_29 WBLb_21 RBL1_19 RBL1_27
+ RBL1_3 WBLb_5 WBLb_13 RBL1_11 WBL_24 WBL_16 RBL1_18 RBL1_26 WBL_8 RBL1_2 RBL1_10 WBL_0 WBLb_26 RBL0_29
+ WBLb_18 RBL0_21 WBLb_10 RBL0_5 RBL0_13 WBLb_2 RBL1_25 WBLb_25 WBLb_17 RBL1_17 WBLb_9 RBL1_1 WBLb_1 RBL1_9
+ WBLb_24 WBLb_16 RBL1_23 RBL1_31 WBLb_0 WBLb_8 RBL1_7 RBL1_15 WBL_29 WBL_21 RBL0_17 RBL0_25 WBL_5 RBL0_1
+ WBL_13 RBL0_9 RBL0_28 WBLb_28 WBLb_20 RBL0_20 WBLb_12 WBLb_4 RBL0_4 RBL0_12 RBL0_27 WBL_30 WBL_22 RBL0_19
+ WBL_14 RBL0_11 WBL_6 RBL0_3 RBL1_24 WBLb_27 WBLb_19 RBL1_16 WBLb_11 RBL1_8 WBLb_3 RBL1_0 RBL0_24 WBLb_31
+ WBLb_23 RBL0_16 RBL0_8 WBLb_15 RBL0_0 WBLb_7 WWL RWL VDD GND

x1 WWL RWL
+ WBL_0 WBL_1 WBL_2 WBL_3 WBL_4 WBL_5 WBL_6 WBL_7
+ WBLb_0 WBLb_1 WBLb_2 WBLb_3 WBLb_4 WBLb_5 WBLb_6 WBLb_7
+ RBL0_0 RBL0_1 RBL0_2 RBL0_3 RBL0_4 RBL0_5 RBL0_6 RBL0_7
+ RBL1_0 RBL1_1 RBL1_2 RBL1_3 RBL1_4 RBL1_5 RBL1_6 RBL1_7
+ VDD GND 10T_1x8_xschem

x2 WWL RWL
+ WBL_8 WBL_9 WBL_10 WBL_11 WBL_12 WBL_13 WBL_14 WBL_15
+ WBLb_8 WBLb_9 WBLb_10 WBLb_11 WBLb_12 WBLb_13 WBLb_14 WBLb_15
+ RBL0_8 RBL0_9 RBL0_10 RBL0_11 RBL0_12 RBL0_13 RBL0_14 RBL0_15
+ RBL1_8 RBL1_9 RBL1_10 RBL1_11 RBL1_12 RBL1_13 RBL1_14 RBL1_15
+ VDD GND 10T_1x8_xschem

x3 WWL RWL
+ WBL_16 WBL_17 WBL_18 WBL_19 WBL_20 WBL_21 WBL_22 WBL_23
+ WBLb_16 WBLb_17 WBLb_18 WBLb_19 WBLb_20 WBLb_21 WBLb_22 WBLb_23
+ RBL0_16 RBL0_17 RBL0_18 RBL0_19 RBL0_20 RBL0_21 RBL0_22 RBL0_23
+ RBL1_16 RBL1_17 RBL1_18 RBL1_19 RBL1_20 RBL1_21 RBL1_22 RBL1_23
+ VDD GND 10T_1x8_xschem

x4 WWL RWL
+ WBL_24 WBL_25 WBL_26 WBL_27 WBL_28 WBL_29 WBL_30 WBL_31
+ WBLb_24 WBLb_25 WBLb_26 WBLb_27 WBLb_28 WBLb_29 WBLb_30 WBLb_31
+ RBL0_24 RBL0_25 RBL0_26 RBL0_27 RBL0_28 RBL0_29 RBL0_30 RBL0_31
+ RBL1_24 RBL1_25 RBL1_26 RBL1_27 RBL1_28 RBL1_29 RBL1_30 RBL1_31
+ VDD GND 10T_1x8_xschem
.ends


* expanding symbol: 10T_1x8_xschem.sym # of pins=34
** sym_path: /home/rjridle/osu-toy-sram/xschem/10T_1x8_xschem.sym
** sch_path: /home/rjridle/osu-toy-sram/xschem/10T_1x8_xschem.sch
.subckt 10T_1x8_xschem WWL RWL
+ WBL_0 WBL_1 WBL_2 WBL_3 WBL_4 WBL_5 WBL_6 WBL_7
+ WBLb_0 WBLb_1 WBLb_2 WBLb_3 WBLb_4 WBLb_5 WBLb_6 WBLb_7
+ RBL0_0 RBL0_1 RBL0_2 RBL0_3 RBL0_4 RBL0_5 RBL0_6 RBL0_7
+ RBL1_0 RBL1_1 RBL1_2 RBL1_3 RBL1_4 RBL1_5 RBL1_6 RBL1_7
+ VDD GND

x1 WWL WBL_0 RBL0_0 RBL1_0 WBLb_0 RWL RWL VDD GND 10T_toy_xschem
x2 WWL WBL_1 RBL0_1 RBL1_1 WBLb_1 RWL RWL VDD GND 10T_toy_xschem
x3 WWL WBL_2 RBL0_2 RBL1_2 WBLb_2 RWL RWL VDD GND 10T_toy_xschem
x4 WWL WBL_3 RBL0_3 RBL1_3 WBLb_3 RWL RWL VDD GND 10T_toy_xschem
x5 WWL WBL_4 RBL0_4 RBL1_4 WBLb_4 RWL RWL VDD GND 10T_toy_xschem
x6 WWL WBL_5 RBL0_5 RBL1_5 WBLb_5 RWL RWL VDD GND 10T_toy_xschem
x7 WWL WBL_6 RBL0_6 RBL1_6 WBLb_6 RWL RWL VDD GND 10T_toy_xschem
x8 WWL WBL_7 RBL0_7 RBL1_7 WBLb_7 RWL RWL VDD GND 10T_toy_xschem
.ends


* expanding symbol: 10T_toy_xschem.sym # of pins=7
** sym_path: /home/rjridle/osu-toy-sram/xschem/10T_toy_xschem.sym
** sch_path: /home/rjridle/osu-toy-sram/xschem/10T_toy_xschem.sch
.subckt 10T_toy_xschem WWL WBL RBL0 RBL1 WBLb RWL0 RWL1 VDD GND
*.PININFO WWL:I RWL0:I RWL1:I WBL:I WBLb:I RBL0:O RBL1:O
x1 net1 net2 VDD GND INVX1
x2 net2 net1 VDD GND INVX1
XM1 net2 WWL WBL GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM2 WBLb WWL net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM3 net3 net2 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM4 RBL0 RWL0 net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM5 net4 net1 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM6 RBL1 RWL1 net4 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
.ends


* expanding symbol: INVX1.sym # of pins=2
** sym_path: /home/rjridle/osu-toy-sram/xschem/INVX1.sym
** sch_path: /home/rjridle/osu-toy-sram/xschem/INVX1.sch
.subckt INVX1 Y A VDD GND
*.PININFO A:I Y:O
XM1 Y A GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM2 Y A VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1
.ends

.end

@ -0,0 +1,58 @@
Flattening unmatched subcell INVX1 in circuit 10T_toy_xschem (1)(2 instances)
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 has no definition, treated as a black box.
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 has no definition, treated as a black box.

Subcircuit pins:
Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8
-------------------------------------------|-------------------------------------------
1 |1
2 |2
3 |3
4 |4
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.
Warning: Equate pins: cell sky130_fd_pr__pfet_01v8 has no definition, treated as a black box.
Warning: Equate pins: cell sky130_fd_pr__pfet_01v8 has no definition, treated as a black box.

Subcircuit pins:
Circuit 1: sky130_fd_pr__pfet_01v8 |Circuit 2: sky130_fd_pr__pfet_01v8
-------------------------------------------|-------------------------------------------
1 |1
2 |2
3 |3
4 |4
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__pfet_01v8 and sky130_fd_pr__pfet_01v8 are equivalent.

Subcircuit summary:
Circuit 1: x10T_toy_magic |Circuit 2: 10T_toy_xschem
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8 (2) |sky130_fd_pr__pfet_01v8 (2)
sky130_fd_pr__nfet_01v8 (8) |sky130_fd_pr__nfet_01v8 (8)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Circuits match correctly.

Subcircuit pins:
Circuit 1: x10T_toy_magic |Circuit 2: 10T_toy_xschem
-------------------------------------------|-------------------------------------------
WBLb |WBLb
WBL |WBL
RBL1 |RBL1
RBL0 |RBL0
RWL1 |RWL1
RWL0 |RWL0
WWL |WWL
GND |(no matching pin)
VDD |(no matching pin)
VDD |(no matching pin)
GND |(no matching pin)
---------------------------------------------------------------------------------------
Cell pin lists for x10T_toy_magic and 10T_toy_xschem altered to match.
Cells failed matching, or top level cell failed pin matching.

@ -0,0 +1,16 @@
* HSPICE file created from 10T_toy_magic.ext - technology: sky130

.subckt x10T_toy_magic WWL RWL0 RWL1 WBL WBLb RBL0 RBL1 VDD GND
X0 junc0 junc1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
X1 GND junc0 junc1 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
X2 RWL0_junc junc0 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
X3 VDD junc0 junc1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.15
X4 WBL WWL junc0 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
X5 junc1 WWL WBLb GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
X6 GND junc1 RWL1_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
X7 RBL0 RWL0 RWL0_junc GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
X8 junc0 junc1 GND GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
X9 RWL1_junc RWL1 RBL1 GND sky130_fd_pr__nfet_01v8 w=1 l=0.15
.ends

** hspice subcircuit dictionary

@ -0,0 +1,23 @@
** sch_path: /home/rjridle/osu-toy-sram/xschem/10T_toy_xschem.sch
.subckt 10T_toy_xschem WWL RWL0 RWL1 WBL WBLb RBL0 RBL1
*.PININFO WWL:I RWL0:I RWL1:I WBL:I WBLb:I RBL0:O RBL1:O
x1 net1 net2 VDD GND INVX1
x2 net2 net1 VDD GND INVX1
XM1 net2 WWL WBL GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM2 WBLb WWL net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM3 net3 net2 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM4 RBL0 RWL0 net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM5 net4 net1 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM6 RBL1 RWL1 net4 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
.ends

* expanding symbol: INVX1.sym # of pins=2
** sym_path: /home/rjridle/osu-toy-sram/xschem/INVX1.sym
** sch_path: /home/rjridle/osu-toy-sram/xschem/INVX1.sch
.subckt INVX1 Y A VDD GND
*.PININFO A:I Y:O
XM1 Y A GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1
XM2 Y A VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1
.ends

.end

File diff suppressed because it is too large Load Diff

@ -0,0 +1,53 @@
Netgen 1.5.206 compiled on Tue Oct 26 17:17:30 CDT 2021
Warning: netgen command 'format' use fully-qualified name '::netgen::format'
Warning: netgen command 'global' use fully-qualified name '::netgen::global'
Reading netlist file ../magic/x10T_32x32_magic.spice
Call to undefined subcircuit x10T_1x8_magic
Creating placeholder cell definition.
Reading netlist file ../xschem/10T_32x32_xschem.spice
Call to undefined subcircuit 10T_1x32_xschem
Creating placeholder cell definition.
Call to undefined subcircuit 10T_1x8_xschem
Creating placeholder cell definition.
Call to undefined subcircuit 10T_toy_xschem
Creating placeholder cell definition.
Call to undefined subcircuit INVX1
Creating placeholder cell definition.
Call to undefined subcircuit sky130_fd_pr__nfet_01v8
Creating placeholder cell definition.
Call to undefined subcircuit sky130_fd_pr__pfet_01v8
Creating placeholder cell definition.
No property area found for device c
Comparison output logged to file comp.out
Logging to file "comp.out" enabled
Contents of circuit 1: Circuit: 'x10T_32x32_magic'
Circuit x10T_32x32_magic contains 353 device instances.
Class: c instances: 225
Class: x10T_1x8_magic instances: 128
Circuit contains 413 nets.
Contents of circuit 2: Circuit: '10T_32x32_xschem'
Circuit 10T_32x32_xschem contains 10240 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 8192
Class: sky130_fd_pr__pfet_01v8 instances: 2048
Circuit contains 4290 nets.

Circuit was modified by parallel/series device merging.
New circuit summary:

Contents of circuit 1: Circuit: 'x10T_32x32_magic'
Circuit x10T_32x32_magic contains 323 device instances.
Class: c instances: 195
Class: x10T_1x8_magic instances: 128
Circuit contains 383 nets.
Contents of circuit 2: Circuit: '10T_32x32_xschem'
Circuit 10T_32x32_xschem contains 10240 device instances.
Class: sky130_fd_pr__nfet_01v8 instances: 8192
Class: sky130_fd_pr__pfet_01v8 instances: 2048
Circuit contains 4290 nets.

Circuit 1 contains 323 devices, Circuit 2 contains 10240 devices. *** MISMATCH ***
Circuit 1 contains 383 nets, Circuit 2 contains 4290 nets. *** MISMATCH ***

Result: Netlists do not match.
Logging to file "comp.out" disabled
LVS Done.

@ -0,0 +1,6 @@
#!/bin/sh
netgen -noc << EOF
permute transistors
lvs $1 $2
quit
EOF

@ -0,0 +1,18 @@
#!/bin/sh
CELL1=$(basename "$1" .spice)
CELL2=$(basename "$2" .spice)
##
# ./runlvs_single 10T_32x32_magic_flattened.spice 10T_32x32_xschem.spice
# $1 = 10T_32x32_magic_flattened.spice
# $2 = 10T_32x32_xschem.spice
#
# CELL1 = 10T_32x32_magic_flattened
# CELL2 = 10T_32x32_xschem
#
#
##

netgen -noc << EOF
lvs "$1 x$CELL1" "$2 $CELL2" sky130A_setup.tcl $CELL1.out
quit
EOF

@ -0,0 +1,449 @@
#---------------------------------------------------------------
# Setup file for netgen LVS
# SkyWater sky130A
#---------------------------------------------------------------
permute default
property default
property parallel none

# Allow override of default #columns in the output format.
catch {format $env(NETGEN_COLUMNS)}

#---------------------------------------------------------------
# For the following, get the cell lists from
# circuit1 and circuit2.
#---------------------------------------------------------------

set cells1 [cells list -all -circuit1]
set cells2 [cells list -all -circuit2]

# NOTE: In accordance with the LVS manager GUI, the schematic is
# always circuit2, so some items like property "par1" only need to
# be specified for circuit2.

#-------------------------------------------
# Resistors (except metal)
#-------------------------------------------

set devices {}
lappend devices sky130_fd_pr__res_iso_pw
lappend devices sky130_fd_pr__res_high_po_0p35
lappend devices sky130_fd_pr__res_high_po_0p69
lappend devices sky130_fd_pr__res_high_po_1p41
lappend devices sky130_fd_pr__res_high_po_2p85
lappend devices sky130_fd_pr__res_high_po_5p73
lappend devices sky130_fd_pr__res_high_po
lappend devices sky130_fd_pr__res_xhigh_po_0p35
lappend devices sky130_fd_pr__res_xhigh_po_0p69
lappend devices sky130_fd_pr__res_xhigh_po_1p41
lappend devices sky130_fd_pr__res_xhigh_po_2p85
lappend devices sky130_fd_pr__res_xhigh_po_5p73
lappend devices sky130_fd_pr__res_xhigh_po
lappend devices sky130_fd_pr__res_generic_nd
lappend devices sky130_fd_pr__res_generic_pd
lappend devices sky130_fd_pr__res_generic_nd__hv
lappend devices sky130_fd_pr__res_generic_pd__hv
lappend devices mrdn_hv mrdp_hv

foreach dev $devices {
if {[lsearch $cells1 $dev] >= 0} {
permute "-circuit1 $dev" 1 2
property "-circuit1 $dev" series enable
property "-circuit1 $dev" series {w critical}
property "-circuit1 $dev" series {l add}
property "-circuit1 $dev" parallel enable
property "-circuit1 $dev" parallel {l critical}
property "-circuit1 $dev" parallel {w add}
property "-circuit1 $dev" parallel {value par}
property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
# Ignore these properties
property "-circuit1 $dev" delete mult
}
if {[lsearch $cells2 $dev] >= 0} {
permute "-circuit2 $dev" 1 2
property "-circuit2 $dev" series enable
property "-circuit2 $dev" series {w critical}
property "-circuit2 $dev" series {l add}
property "-circuit2 $dev" parallel enable
property "-circuit2 $dev" parallel {l critical}
property "-circuit2 $dev" parallel {w add}
property "-circuit2 $dev" parallel {value par}
property "-circuit2 $dev" tolerance {l 0.01} {w 0.01}
# Ignore these properties
property "-circuit2 $dev" delete mult
}
}

#-------------------------------------------
# MRM (metal) resistors and poly resistor
#-------------------------------------------

set devices {}
lappend devices sky130_fd_pr__res_generic_po
lappend devices sky130_fd_pr__res_generic_l1
lappend devices sky130_fd_pr__res_generic_m1
lappend devices sky130_fd_pr__res_generic_m2
lappend devices sky130_fd_pr__res_generic_m3
lappend devices sky130_fd_pr__res_generic_m4
lappend devices sky130_fd_pr__res_generic_m5

foreach dev $devices {
if {[lsearch $cells1 $dev] >= 0} {
permute "-circuit1 $dev" end_a end_b
property "-circuit1 $dev" series enable
property "-circuit1 $dev" series {w critical}
property "-circuit1 $dev" series {l add}
property "-circuit1 $dev" parallel enable
property "-circuit1 $dev" parallel {l critical}
property "-circuit1 $dev" parallel {w add}
property "-circuit1 $dev" parallel {value par}
property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
# Ignore these properties
property "-circuit1 $dev" delete mult
}
if {[lsearch $cells2 $dev] >= 0} {
permute "-circuit2 $dev" end_a end_b
property "-circuit2 $dev" series enable
property "-circuit2 $dev" series {w critical}
property "-circuit2 $dev" series {l add}
property "-circuit2 $dev" parallel enable
property "-circuit2 $dev" parallel {l critical}
property "-circuit2 $dev" parallel {w add}
property "-circuit2 $dev" parallel {value par}
property "-circuit2 $dev" tolerance {l 0.01} {w 0.01}
# Ignore these properties
property "-circuit2 $dev" delete mult
}
}

#-------------------------------------------
# (MOS) transistors
#-------------------------------------------

set devices {}
lappend devices sky130_fd_pr__nfet_01v8
lappend devices sky130_fd_pr__nfet_01v8_lvt
lappend devices sky130_fd_bs_flash__special_sonosfet_star
lappend devices sky130_fd_pr__nfet_g5v0d10v5
lappend devices sky130_fd_pr__nfet_05v0_nvt
lappend devices sky130_fd_pr__pfet_01v8
lappend devices sky130_fd_pr__pfet_01v8_lvt
lappend devices sky130_fd_pr__pfet_01v8_mvt
lappend devices sky130_fd_pr__pfet_01v8_hvt
lappend devices sky130_fd_pr__pfet_g5v0d10v5
lappend devices sky130_fd_pr__special_pfet_pass
lappend devices sky130_fd_pr__special_nfet_pass
lappend devices sky130_fd_pr__special_nfet_latch
lappend devices sky130_fd_pr__cap_var_lvt
lappend devices sky130_fd_pr__cap_var_hvt
lappend devices sky130_fd_pr__cap_var
lappend devices sky130_fd_pr__nfet_20v0_nvt
lappend devices sky130_fd_pr__nfet_20v0
lappend devices sky130_fd_pr__pfet_20v0

foreach dev $devices {
if {[lsearch $cells1 $dev] >= 0} {
permute "-circuit1 $dev" 1 3
property "-circuit1 $dev" parallel enable
property "-circuit1 $dev" parallel {l critical}
property "-circuit1 $dev" parallel {w add}
property "-circuit1 $dev" tolerance {w 0.01} {l 0.01}
# Ignore these properties
property "-circuit1 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography
}
if {[lsearch $cells2 $dev] >= 0} {
permute "-circuit2 $dev" 1 3
property "-circuit2 $dev" parallel enable
property "-circuit2 $dev" parallel {l critical}
property "-circuit2 $dev" parallel {w add}
property "-circuit2 $dev" tolerance {w 0.01} {l 0.01}
# Ignore these properties
property "-circuit2 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography
}
}

#---------------------------------------------------------------------
# (MOS) ESD transistors. Note that the ESD transistors have a flanged
# gate. Magic disagrees slightly on how to interpret the width of the
# devices, so the tolerance is increased to 7% to cover the difference
#---------------------------------------------------------------------

lappend devices sky130_fd_pr__esd_nfet_g5v0d10v5
lappend devices sky130_fd_pr__esd_pfet_g5v0d10v5

foreach dev $devices {
if {[lsearch $cells1 $dev] >= 0} {
permute "-circuit1 $dev" 1 3
property "-circuit1 $dev" parallel enable
property "-circuit1 $dev" parallel {l critical}
property "-circuit1 $dev" parallel {w add}
property "-circuit1 $dev" tolerance {w 0.07} {l 0.01}
# Ignore these properties
property "-circuit1 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography
}
if {[lsearch $cells2 $dev] >= 0} {
permute "-circuit2 $dev" 1 3
property "-circuit2 $dev" parallel enable
property "-circuit2 $dev" parallel {l critical}
property "-circuit2 $dev" parallel {w add}
property "-circuit2 $dev" tolerance {w 0.07} {l 0.01}
# Ignore these properties
property "-circuit2 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography
}
}

#-------------------------------------------
# diodes
#-------------------------------------------

set devices {}
lappend devices sky130_fd_pr__diode_pw2nd_05v5
lappend devices sky130_fd_pr__diode_pw2nd_05v5_lvt
lappend devices sky130_fd_pr__diode_pw2nd_05v5_nvt
lappend devices sky130_fd_pr__diode_pd2nw_05v5
lappend devices sky130_fd_pr__diode_pd2nw_05v5_lvt
lappend devices sky130_fd_pr__diode_pd2nw_05v5_hvt
lappend devices sky130_fd_pr__diode_pw2nd_11v0
lappend devices sky130_fd_pr__diode_pd2nw_11v0

foreach dev $devices {
if {[lsearch $cells1 $dev] >= 0} {
property "-circuit1 $dev" parallel enable
property "-circuit1 $dev" parallel {area add}
property "-circuit1 $dev" parallel {value add}
property "-circuit1 $dev" tolerance {area 0.02}
# Ignore these properties
property "-circuit1 $dev" delete mult perim
}
if {[lsearch $cells2 $dev] >= 0} {
property "-circuit2 $dev" parallel enable
property "-circuit2 $dev" parallel {area add}
property "-circuit2 $dev" parallel {value add}
property "-circuit2 $dev" tolerance {area 0.02}
# Ignore these properties
property "-circuit2 $dev" delete mult perim
}
}

#-------------------------------------------
# capacitors
# MiM capacitors
#-------------------------------------------

set devices {}
lappend devices sky130_fd_pr__cap_mim_m3_1
lappend devices sky130_fd_pr__cap_mim_m3_2

foreach dev $devices {
if {[lsearch $cells1 $dev] >= 0} {
property "-circuit1 $dev" parallel enable
property "-circuit1 $dev" parallel {area add}
property "-circuit1 $dev" parallel {value add}
property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
# Ignore these properties
property "-circuit1 $dev" delete mult perim mf
}
if {[lsearch $cells2 $dev] >= 0} {
property "-circuit2 $dev" parallel enable
property "-circuit2 $dev" parallel {area add}
property "-circuit2 $dev" parallel {value add}
property "-circuit2 $dev" tolerance {l 0.01} {w 0.01}
# Ignore these properties
property "-circuit2 $dev" delete mult perim mf
}
}

#-------------------------------------------
# Fixed-layout devices
# bipolar transistors,
# VPP capacitors
#-------------------------------------------

set devices {}
lappend devices sky130_fd_pr__npn_05v5_W1p00L1p00
lappend devices sky130_fd_pr__npn_05v5_W1p00L2p00
lappend devices sky130_fd_pr__pnp_05v5_W0p68L0p68
lappend devices sky130_fd_pr__pnp_05v5_W3p40L3p40
lappend devices sky130_fd_pr__npn_05v5
lappend devices sky130_fd_pr__pnp_05v5
lappend devices sky130_fd_pr__npn_11v0

lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_lim5_shield
lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m3_lim5_shield
lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m4_shield
lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_pom4_shield
lappend devices sky130_fd_pr__cap_vpp_4p4x4p6_m3_lim5_shield
lappend devices sky130_fd_pr__cap_vpp_6p8x6p1_lim4_shield
lappend devices sky130_fd_pr__cap_vpp_6p8x6p1_polym4_shield
lappend devices sky130_fd_pr__cap_vpp_8p6x7p9_m3_lim5_shield
lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m3_li_shield
lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m3_shield
lappend devices sky130_fd_pr__cap_vpp_1p8x1p8_li_shield
lappend devices sky130_fd_pr__cap_vpp_1p8x1p8_m3_shield
lappend devices sky130_fd_pr__cap_vpp_4p4x4p6_m3_li_shield
lappend devices sky130_fd_pr__cap_vpp_4p4x4p6_m3_shield
lappend devices sky130_fd_pr__cap_vpp_8p6x7p9_m3_li_shield
lappend devices sky130_fd_pr__cap_vpp_8p6x7p9_m3_shield
lappend devices sky130_fd_pr__ind_04_01
lappend devices sky130_fd_pr__ind_04_02

foreach dev $devices {
if {[lsearch $cells1 $dev] >= 0} {
property "-circuit1 $dev" parallel enable
# Ignore these properties
property "-circuit1 $dev" delete mult
}
if {[lsearch $cells2 $dev] >= 0} {
property "-circuit2 $dev" parallel enable
# Ignore these properties
property "-circuit2 $dev" delete mult
}
}

#---------------------------------------------------------------
# Schematic cells which are not extractable
#---------------------------------------------------------------

set devices {sky130_fd_io__condiode sky130_fd_io__tap_1}

foreach dev $devices {
if {[lsearch $cells1 $dev] >= 0} {
ignore class "-circuit1 $dev"
}
if {[lsearch $cells2 $dev] >= 0} {
ignore class "-circuit2 $dev"
}
}

#---------------------------------------------------------------
# Digital cells (ignore decap, fill, and tap cells)
# Make a separate list for each supported library
#---------------------------------------------------------------
# e.g., ignore class "-circuit2 sky130_fc_sc_hd__decap_3"
#---------------------------------------------------------------

if { [info exist ::env(MAGIC_EXT_USE_GDS)] && $::env(MAGIC_EXT_USE_GDS) } {
foreach cell $cells1 {
# if {[regexp {sky130_fd_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
# ignore class "-circuit1 $cell"
# }
if {[regexp {sky130_fd_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
ignore class "-circuit1 $cell"
}
if {[regexp {sky130_fd_sc_[^_]+__tapvpwrvgnd_[[:digit:]]+} $cell match]} {
ignore class "-circuit1 $cell"
}
if {[regexp {sky130_ef_sc_[^_]+__fakediode_[[:digit:]]+} $cell match]} {
ignore class "-circuit1 $cell"
}
}
foreach cell $cells2 {
# if {[regexp {sky130_fd_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
# ignore class "-circuit2 $cell"
# }
if {[regexp {sky130_fd_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
ignore class "-circuit2 $cell"
}
if {[regexp {sky130_fd_sc_[^_]+__tapvpwrvgnd_[[:digit:]]+} $cell match]} {
ignore class "-circuit2 $cell"
}
if {[regexp {sky130_ef_sc_[^_]+__fakediode_[[:digit:]]+} $cell match]} {
ignore class "-circuit2 $cell"
}
}
}

#---------------------------------------------------------------
# Allow the fill, decap, etc., cells to be parallelized
#---------------------------------------------------------------

foreach cell $cells1 {
if {[regexp {sky130_fd_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
property "-circuit1 $cell" parallel enable
}
if {[regexp {sky130_fd_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
property "-circuit1 $cell" parallel enable
}
if {[regexp {sky130_fd_sc_[^_]+__tapvpwrvgnd_[[:digit:]]+} $cell match]} {
property "-circuit1 $cell" parallel enable
}
if {[regexp {sky130_fd_sc_[^_]+__diode_[[:digit:]]+} $cell match]} {
property "-circuit1 $cell" parallel enable
}
if {[regexp {sky130_fd_sc_[^_]+__fill_diode_[[:digit:]]+} $cell match]} {
property "-circuit1 $cell" parallel enable
}
if {[regexp {sky130_ef_sc_[^_]+__fakediode_[[:digit:]]+} $cell match]} {
property "-circuit1 $cell" parallel enable
}
}
foreach cell $cells2 {
if {[regexp {sky130_fd_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
property "-circuit2 $cell" parallel enable
}
if {[regexp {sky130_fd_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
property "-circuit2 $cell" parallel enable
}
if {[regexp {sky130_fd_sc_[^_]+__tapvpwrvgnd_[[:digit:]]+} $cell match]} {
property "-circuit2 $cell" parallel enable
}
if {[regexp {sky130_fd_sc_[^_]+__diode_[[:digit:]]+} $cell match]} {
property "-circuit2 $cell" parallel enable
}
if {[regexp {sky130_fd_sc_[^_]+__fill_diode_[[:digit:]]+} $cell match]} {
property "-circuit2 $cell" parallel enable
}
if {[regexp {sky130_ef_sc_[^_]+__fakediode_[[:digit:]]+} $cell match]} {
property "-circuit2 $cell" parallel enable
}
}

#---------------------------------------------------------------
# Handle cells captured from Electric
#
# Find cells of the form "<library>__<cellname>" in the netlist
# from Electric where the extracted layout netlist has only
# "<cellname>". Cross-check by ensuring that the full name
# "<library>__<cellname>" does not exist in both cells, and that
# the truncated name "<cellname>" does not exist in both cells.
#---------------------------------------------------------------
# e.g., hydra_spi_controller__hydra_spi_controller
#---------------------------------------------------------------

foreach cell $cells1 {
if {[regexp "(.+)__(.+)" $cell match library cellname]} {
if {([lsearch $cells2 $cell] < 0) && \
([lsearch $cells2 $cellname] >= 0) && \
([lsearch $cells1 $cellname] < 0)} {
equate classes "-circuit1 $cell" "-circuit2 $cellname"
puts stdout "Matching pins of $cell in circuit 1 and $cellname in circuit 2"
equate pins "-circuit1 $cell" "-circuit2 $cellname"
}
}
}

foreach cell $cells2 {
if {[regexp "(.+)__(.+)" $cell match library cellname]} {
if {([lsearch $cells1 $cell] < 0) && \
([lsearch $cells1 $cellname] >= 0) && \
([lsearch $cells2 $cellname] < 0)} {
equate classes "-circuit1 $cellname" "-circuit2 $cell"
puts stdout "Matching pins of $cellname in circuit 1 and $cell in circuit 2"
equate pins "-circuit1 $cellname" "-circuit2 $cell"
}
}
}

# Match pins on black-box cells if LVS is called with "-blackbox"
if {[model blackbox]} {
foreach cell $cells1 {
if {[model "-circuit1 $cell"] == "blackbox"} {
if {[lsearch $cells2 $cell] >= 0} {
puts stdout "Matching pins of $cell in circuits 1 and 2"
equate pins "-circuit1 $cell" "-circuit2 $cell"
}
}
}
}

#---------------------------------------------------------------

@ -0,0 +1,76 @@
###
### Source file sky130.magicrc
### Process this file with the m4 processor
###


# MUST CHANGE THIS TO REPOSITORIES TOP LEVEL DIRECTORY
set PDK_ROOT /path/to/osu-toy-sram


puts stdout "Sourcing design .magicrc for technology sky130 ..."

# Put grid on 0.005 pitch. This is important, as some commands don't
# rescale the grid automatically (such as lef read?).

set scalefac [tech lambda]
if {[lindex $scalefac 1] < 2} {
scalegrid 1 2
}

# drc off
drc euclidean on

# Change this to a fixed number for repeatable behavior with GDS writes
# e.g., "random seed 12345"
catch {random seed}

# Turn off the scale option on ext2spice or else it conflicts with the
# scale in the model files.
ext2spice scale off


# Set this to the folder that holds the technology files
set TECH_ROOT ${PDK_ROOT}/magic/.magic_tech

# loading technology
tech load ${TECH_ROOT}/sky130A.tech
# load device generator
#source $TECH_ROOT/sky130.tcl

# load bind keys (optional)
source ${TECH_ROOT}/sky130.BindKeys

# set units to lambda grid
snap internal

# set sky130 standard power, ground, and substrate names
set VDD VPWR
set GND VGND
set SUB VSUBS

# add path to IP from catalog. This procedure defined in the PDK script.
catch {magic::query_mylib_ip}
# add path to local IP from user design space. Defined in the PDK script.
catch {magic::query_my_projects}

# Custom macros
#macro XK_Left "scroll l .1 w"
#macro Shift_XK_Left "scroll l 1 w"
#macro Control_XK_Left "box grow w 1"
#macro Control_Shift_XK_Left "box shrink e 1"
#macro XK_Right "scroll r .1 w"
#macro Shift_XK_Right "scroll r 1 w"
#macro Control_XK_Right "box grow e 1"
#macro Control_Shift_XK_Right "box shrink w 1"
#macro XK_Up "scroll u .1 w"
#macro Shift_XK_Up "scroll u 1 w"
#macro Control_XK_Up "box grow n 1"
#macro Control_Shift_XK_Up "box shrink s 1"
#macro XK_Down "scroll d .1 w"
#macro Shift_XK_Down "scroll d 1 w"
#macro Control_XK_Down "box grow s 1"
#macro Control_Shift_XK_Down "box shrink n 1"
#macro XK_Pointer_Button4 "scroll u .05 w"
#macro XK_Pointer_Button5 "scroll d .05 w"
#macro . "history redo -1"

@ -0,0 +1,30 @@
# Custom macros
macro z "findbox zoom"
macro f "select top cell ; view"
macro q "move left 1"
macro w "move down 1"
macro e "move up 1"
macro r "move right 1"
macro Q "stretch left 1"
macro W "stretch down 1"
macro E "stretch up 1"
macro R "stretch right 1"
macro XK_Left "scroll l .1 w"
macro Shift_XK_Left "scroll l 1 w"
macro Control_XK_Left "box grow w 1"
macro Control_Shift_XK_Left "box shrink e 1"
macro XK_Right "scroll r .1 w"
macro Shift_XK_Right "scroll r 1 w"
macro Control_XK_Right "box grow e 1"
macro Control_Shift_XK_Right "box shrink w 1"
macro XK_Up "scroll u .1 w"
macro Shift_XK_Up "scroll u 1 w"
macro Control_XK_Up "box grow n 1"
macro Control_Shift_XK_Up "box shrink s 1"
macro XK_Down "scroll d .1 w"
macro Shift_XK_Down "scroll d 1 w"
macro Control_XK_Down "box grow s 1"
macro Control_Shift_XK_Down "box shrink n 1"
macro XK_Pointer_Button4 "scroll u .05 w"
macro XK_Pointer_Button5 "scroll d .05 w"
macro . "history redo -1"

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

@ -0,0 +1,763 @@
#undef RERAM
tech
format 32
TECHNAME-GDS
end

version
version REVISION
description "SkyWater SKY130: Vendor GDS layers and supplementary DRC"
requires magic-8.3.124
end

planes
p1
p2
p3
p4
p5
p6
p7
p8
p9
p10
p11
p12
p13
p14
p15
p16
p17
p18
p19
p20
p21
p22
p23
p24
p25
p26
p27
p28
p29
p30
p31
p32
p33
p34
p35
p36
p37
p38
p39
p40
p41
p42
p43
end

types
p1 NWELL,l1
p1 NWELLT,l60
p1 NWELLP,l62
p2 DNWELL,l2
p3 DIFF,l3
p3 TAP,l4
p4 LVTN,l5
p4 HVTP,l6
p5 HVI,l7
p6 TUNM,l8
p7 POLY,l9
p7 POLYP,l63
p7 POLYT,l70
p8 NPC,l10
p9 PSDM,l11
p9 NSDM,l12
p10 LICON1,l13
p11 LI1,l14
p11 LI1T,l15
p11 LI1P,l16
p12 MCON,l17
p12 MET1,l18
p12 MET1T,l19
p12 MET1P,l20
p13 VIA1,l21
p13 MET2,l22
p13 MET2T,l23
p13 MET2P,l24
p14 VIA2,l25
p14 MET3,l26
p14 MET3T,l27
p14 MET3P,l28
p15 VIA3,l29
p15 MET4,l30
p15 MET4T,l31
p15 MET4P,l32
p16 VIA4,l33
p16 MET5,l34
p16 MET5T,l35
p16 MET5P,l36
p17 PAD,l37
p17 PADT,l38
p17 PADP,l39
p18 AREAID,l40
p19 TEXT,l41
p20 HVTR,l42
p21 NCM,l43
p22 RPM,l44
p23 NSM,l45
p24 RDL,l46
p25 VHVI,l47
p26 LDNTM,l48
p26 HVNTM,l49
p27 PMM,l50
p28 PNP,l51
p29 CAP,l52
p30 IND,l53
p31 PWRES,l54
p32 POLYRES,l55
p33 DIFFRES,l56
p34 DIODE,l57
p35 POLYM,l58
p36 COREID,l59
p37 PWELLT,l61
p37 PWELLP,l64
p38 CFOMDROP,l65
p39 CLI1MADD,l66
p40 CNTMADD,l67
p41 CP1MADD,l68
p42 BOUND,l69
p43 RERAM,l71
end

contact
end

styles
styletype mos
l1 nwell
l2 cwell
l3 ndiffusion
l4 pdiffusion
l5 implant1
l6 implant2
l7 implant3
l8 subcircuit
l9 polysilicon
l10 implant4
l11 pdop_stripes
l12 ndop_stripes
l13 obsmetal1 contact_X'es
l14 metal1
l15 metal1
l16 metal1
l17 metal1 metal2 via1
l18 metal2
l19 metal2
l20 metal2
l21 metal2 metal3 via2
l22 metal3
l23 metal3
l24 metal3
l25 metal3 metal4 via3
l26 metal4
l27 metal4
l28 metal4
l29 metal4 metal5 via4
l30 metal5
l31 metal5
l32 metal5
l33 metal5 metal6 via5
l34 metal6
l35 metal6
l36 metal6
l37 overglass
l38 overglass
l39 overglass
l40 subcircuit
l41 comment
l42 implant1
l43 mim_top
l44 mim_bottom
l45 ntransistor_stripes
l46 metal7
l47 electrode
l48 nwell_field_implant
l49 hvndiff_mask
l50 poly_light
l51 mvpdiff
l52 mvndiff
l53 hvpdiff
l54 cwellnsc
l55 poly_resist poly_resist_stripes
l56 ptransistor_stripes
l57 hvpdiff_mask
l58 poly_resist
l59 subcircuit
l60 nwell
l61 pwell
l62 nwell
l63 polysilicon
l64 pwell
l65 implant1
l66 implant2
l67 implant3
l68 implant4
l69 subcircuit
l70 polysilicon
l71 electrode_stripes
error_p error_waffle
error_s error_waffle
error_ps error_waffle
end

compose
paint MCON MET1 MCON
paint VIA1 MET2 VIA1
paint VIA2 MET3 VIA2
paint VIA3 MET4 VIA3
paint VIA4 MET5 VIA4

paint MCON MET1P MCON
paint VIA1 MET2P VIA1
paint VIA2 MET3P VIA2
paint VIA3 MET4P VIA3
paint VIA4 MET5P VIA4

paint MCON MET1T MCON
paint VIA1 MET2T VIA1
paint VIA2 MET3T VIA2
paint VIA3 MET4T VIA3
paint VIA4 MET5T VIA4
end

connect
end

cifoutput
style gdsii
scalefactor 10 nanometers
options calma-permissive-labels
gridlimit 1

layer NWELL NWELL,NWELLT,NWELLP
calma 64 20

layer NWELLT
labels NWELLT noport
calma 64 16

layer NWELLP
labels NWELLP port
calma 64 5

layer DNWELL DNWELL
labels DNWELL
calma 64 18

layer DIFF DIFF
labels DIFF
calma 65 20

layer TAP TAP
labels TAP
calma 65 44

layer POLY POLY,POLYP,POLYT
calma 66 20

layer POLYT
labels POLYT noport
calma 66 16

layer POLYP
labels POLYP port
calma 66 5

layer LVTN LVTN
labels LVTN
calma 125 44

layer HVTP HVTP
labels HVTP
calma 78 44

layer HVI HVI
labels HVI
calma 75 20

layer TUNM TUNM
labels TUNM
calma 80 20

layer NPC NPC
labels NPC
calma 95 20

layer PSDM PSDM
labels PSDM
calma 94 20

layer NSDM NSDM
labels NSDM
calma 93 44

layer LICON1 LICON1
labels LICON1
calma 66 44

# Note: LICON1 not on LI1 plane, may not be coincident with LI1.
layer LI1 LI1,LI1T,LI1P
calma 67 20

layer LI1T
labels LI1T noport
calma 67 16

layer LI1P
labels LI1P port