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<img align="right" src="doc/img/bob_64x64.jpg">
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# ToySRAM
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## A test site for a high-specific-bandwidth memory design
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* We make high-specific-bandwidth multiport memories child’s play
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* We make 10T SRAM a first-class citizen, and use pumping and replication for high frequency and additional ports
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## Description
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The goal is to demonstrate specific bandwidth results from 90nm to 2nm, and use
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the basic design to grow as many ports as necessary through replication, to
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produce more efficient processors and accelerators with *less circuit-design effort*.
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What is specific bandwidth?
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* It measures the read and write bandwidth per unit area
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* Bandwidth per unit area is an analog to specific gravity, which is mass per unit volume
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* It's more encompassing than bit density, which drives complexity to improve bandwidth
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Why does Toy-SRAM do so well?
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* It's enhanced by having a 10T SRAM/2 read ports/1 write port
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* It supports low-cost super-pipelining (2x+ the system frequency, without latch overhead)
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* It enables energy-efficient ultralow-voltage operation by avoiding read disturb
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Specific bandwidth can be expressed with two metrics:
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* Technology dependent “X TB/(sec * mm 2 )”
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* Technology independent “Y 1/(FO4 delay * PC PITCH * min horizontal metal pitch)”
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## Array Design (64x24_2R1W)
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#### 2R1W memory cell
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* read bitlines are the NFET part of a domino stage
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<image src="./cell.png">
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#### Subarray
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* 16 word x 12 bit array of memory cells
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#### 64x24_2R1W 'hard' array
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* (8) subarrays
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* (12) addr/strobe inputs per port are decoded to 64 word lines and precharge enable
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* subarray bitlines are precharged and combined with neighbor subarray in local eval cell
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* final data outs are selected from half-array local evals
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#### 64x24_2R1W 'logical' array
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* strobe plus 6 address lines predecoded to 12 array input lines per port
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* port latching
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### Other
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#### SDR/DDR
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* double-pumping the strobe allows 4R2W operation
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#### LSDL
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* a custom LSDL cell can be used to latch the outputs in the array
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## Links
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* skywater-pdk.slack.com#toysram
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## To Do
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### memory cell
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* schem, layout, spice, liberty files
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* *WRONG!* needs RWL0+RWL1
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### 64x24 array
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* subarray
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* 16x12 gds/lef needed
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* lib also?
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* eval cell
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* can pfet be instantiated in rtl?
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* if not, just create a custom cell just for it (le_pullup); can make
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different strength versions and connect in rtl
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* custom cell; nand2 + pfet pullup gated by precharge for L/R
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* quarter
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* single macro with L/R subarrays and eval stack between
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* then need just decode gap and i/o gap between four quarters
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* full with placed std cell decoders, etc.
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* single macro with placed netlist cells
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### 64x72 array
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* rtl for in/out latching
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* rtl for strobe (sdr, ddr delay taps)
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* rtl for bist?
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* rtl for cfg (strobe)
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### Verif
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* cycle sim for basic 64x72 rtl
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* cycle sim for site
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* spice sim for 16x12 + eval + 16x12 (quarter)?
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### Site
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* ring oscillator?
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* multiarray?
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* scan interface
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* wb interface?
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### Extras
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* auto-convert memory cell and eval to 180 and build site
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* lsdl latch in 64x24 for data outs
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