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// © IBM Corp. 2022
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions & limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make & use the physical chip.
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// Behavioral for 64x24 toysram (sdr or ddr) using 16x12 hard subarrays
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`timescale 1 ps / 1 ps
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// 0: gen 8x 16x12 plus local eval 1: gen 4x 32x24 and no local eval
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module regfile_64x24_2r1w #(
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parameter integer RA_32x24 = 1
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) (
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input rd0_c_na0,
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input rd0_c_a0,
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input rd0_na1_na2,
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input rd0_na1_a2,
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input rd0_a1_na2,
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input rd0_a1_a2,
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input rd0_na3,
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input rd0_a3,
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input rd0_na4_na5,
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input rd0_na4_a5,
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input rd0_a4_na5,
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input rd0_a4_a5,
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output [0:23] rd0_dat,
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input rd1_c_na0,
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input rd1_c_a0,
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input rd1_na1_na2,
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input rd1_na1_a2,
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input rd1_a1_na2,
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input rd1_a1_a2,
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input rd1_na3,
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input rd1_a3,
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input rd1_na4_na5,
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input rd1_na4_a5,
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input rd1_a4_na5,
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input rd1_a4_a5,
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output [0:23] rd1_dat,
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input wr0_c_na0,
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input wr0_c_a0,
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input wr0_na1_na2,
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input wr0_na1_a2,
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input wr0_a1_na2,
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input wr0_a1_a2,
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input wr0_na3,
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input wr0_a3,
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input wr0_na4_na5,
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input wr0_na4_a5,
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input wr0_a4_na5,
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input wr0_a4_a5,
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input [0:23] wr0_dat
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);
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// word & bit selects
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wire [0:15] rwl0_00_15_00_11;
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wire [0:15] rwl0_00_15_12_23;
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wire [0:15] rwl1_00_15_00_11;
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wire [0:15] rwl1_00_15_12_23;
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wire [0:15] wwl_00_15_00_11;
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wire [0:15] wwl_00_15_12_23;
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wire [0:11] rbl0_00_15_00_11;
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wire [0:11] rbl0_00_15_12_23;
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wire [0:11] rbl1_00_15_00_11;
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wire [0:11] rbl1_00_15_12_23;
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wire [0:11] wbl_00_15_00_11;
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wire [0:11] wbl_00_15_12_23;
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wire [0:15] rwl0_16_31_00_11;
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wire [0:15] rwl0_16_31_12_23;
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wire [0:15] rwl1_16_31_00_11;
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wire [0:15] rwl1_16_31_12_23;
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wire [0:15] wwl_16_31_00_11;
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wire [0:15] wwl_16_31_12_23;
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wire [0:11] rbl0_16_31_00_11;
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wire [0:11] rbl0_16_31_12_23;
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wire [0:11] rbl1_16_31_00_11;
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wire [0:11] rbl1_16_31_12_23;
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wire [0:11] wbl_16_31_00_11;
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wire [0:11] wbl_16_31_12_23;
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wire [0:15] rwl0_32_47_00_11;
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wire [0:15] rwl0_32_47_12_23;
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wire [0:15] rwl1_32_47_00_11;
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wire [0:15] rwl1_32_47_12_23;
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wire [0:15] wwl_32_47_00_11;
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wire [0:15] wwl_32_47_12_23;
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wire [0:11] rbl0_32_47_00_11;
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wire [0:11] rbl0_32_47_12_23;
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wire [0:11] rbl1_32_47_00_11;
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wire [0:11] rbl1_32_47_12_23;
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wire [0:11] wbl_32_47_00_11;
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wire [0:11] wbl_32_47_12_23;
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wire [0:15] rwl0_48_63_00_11;
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wire [0:15] rwl0_48_63_12_23;
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wire [0:15] rwl1_48_63_00_11;
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wire [0:15] rwl1_48_63_12_23;
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wire [0:15] wwl_48_63_00_11;
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wire [0:15] wwl_48_63_12_23;
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wire [0:11] rbl0_48_63_00_11;
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wire [0:11] rbl0_48_63_12_23;
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wire [0:11] rbl1_48_63_00_11;
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wire [0:11] rbl1_48_63_12_23;
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wire [0:11] wbl_48_63_00_11;
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wire [0:11] wbl_48_63_12_23;
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// 32x24
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wire [0:11] rbl0_00_31_00_11;
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wire [0:11] rbl0_00_31_12_23;
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wire [0:11] rbl1_00_31_00_11;
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wire [0:11] rbl1_00_31_12_23;
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wire [0:11] wbl_00_31_00_11;
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wire [0:11] wbl_00_31_12_23;
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wire [0:11] rbl0_32_63_00_11;
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wire [0:11] rbl0_32_63_12_23;
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wire [0:11] rbl1_32_63_00_11;
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wire [0:11] rbl1_32_63_12_23;
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wire [0:11] wbl_32_63_00_11;
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wire [0:11] wbl_32_63_12_23;
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generate
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if (RA_32x24 == 0) begin
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// subarray cells; 4x2 16w/12b subarrays
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// words 00:15
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toysram_16x12 r000 (
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.RWL0(rwl0_00_15_00_11),
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.RWL1(rwl1_00_15_00_11),
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.WWL(wwl_00_15_00_11),
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.RBL0(rbl0_00_15_00_11),
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.RBL1(rbl1_00_15_00_11),
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.WBL(wbl_00_15_00_11),
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.WBLb(~wbl_00_15_00_11)
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);
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toysram_16x12 r001 (
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.RWL0(rwl0_00_15_12_23),
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.RWL1(rwl1_00_15_12_23),
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.WWL(wwl_00_15_12_23),
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.RBL0(rbl0_00_15_12_23),
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.RBL1(rbl1_00_15_12_23),
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.WBL(wbl_00_15_12_23),
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.WBLb(~wbl_00_15_12_23)
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);
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// words 16:31
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toysram_16x12 r010 (
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.RWL0(rwl0_16_31_00_11),
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.RWL1(rwl1_16_31_00_11),
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.WWL(wwl_16_31_00_11),
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.RBL0(rbl0_16_31_00_11),
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.RBL1(rbl1_16_31_00_11),
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.WBL(wbl_16_31_00_11),
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.WBLb(~wbl_16_31_00_11)
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);
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toysram_16x12 r011 (
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.RWL0(rwl0_16_31_12_23),
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.RWL1(rwl1_16_31_12_23),
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.WWL(wwl_16_31_12_23),
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.RBL0(rbl0_16_31_12_23),
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.RBL1(rbl1_16_31_12_23),
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.WBL(wbl_16_31_12_23),
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.WBLb(~wbl_16_31_12_23)
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);
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// words 32:47
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toysram_16x12 r100 (
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.RWL0(rwl0_32_47_00_11),
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.RWL1(rwl1_32_47_00_11),
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.WWL(wwl_32_47_00_11),
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.RBL0(rbl0_32_47_00_11),
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.RBL1(rbl1_32_47_00_11),
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.WBL(wbl_32_47_00_11),
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.WBLb(~wbl_32_47_00_11)
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);
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toysram_16x12 r101 (
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.RWL0(rwl0_32_47_12_23),
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.RWL1(rwl1_32_47_12_23),
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.WWL(wwl_32_47_12_23),
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.RBL0(rbl0_32_47_12_23),
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.RBL1(rbl1_32_47_12_23),
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.WBL(wbl_32_47_12_23),
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.WBLb(~wbl_32_47_12_23)
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);
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// words 48:63
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toysram_16x12 r110 (
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.RWL0(rwl0_48_63_00_11),
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.RWL1(rwl1_48_63_00_11),
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.WWL(wwl_48_63_00_11),
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.RBL0(rbl0_48_63_00_11),
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.RBL1(rbl1_48_63_00_11),
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.WBL(wbl_48_63_00_11),
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.WBLb(~wbl_48_63_00_11)
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);
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toysram_16x12 r111 (
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.RWL0(rwl0_48_63_12_23),
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.RWL1(rwl1_48_63_12_23),
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.WWL(wwl_48_63_12_23),
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.RBL0(rbl0_48_63_12_23),
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.RBL1(rbl1_48_63_12_23),
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.WBL(wbl_48_63_12_23),
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.WBLb(~wbl_48_63_12_23)
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);
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end else begin
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// subarray cells; 2x2 32w/24b subarrays w/local eval inside between pairs
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// words 00:31
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toysram_32x12 r00 (
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.RWL0({rwl0_00_15_00_11,rwl0_16_31_00_11}),
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.RWL1({rwl1_00_15_00_11,rwl1_16_31_00_11}),
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.WWL({wwl_00_15_00_11,wwl_16_31_00_11}),
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.RBL0(rbl0_00_31_00_11),
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.RBL1(rbl1_00_31_00_11),
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.WBL(wbl_00_31_00_11),
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.WBLb(~wbl_00_31_00_11)
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);
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toysram_32x12 r01 (
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.RWL0({rwl0_00_15_12_23,rwl0_16_31_12_23}),
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.RWL1({rwl1_00_15_12_23,rwl1_16_31_12_23}),
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.WWL({wwl_00_15_12_23,wwl_16_31_12_23}),
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.RBL0(rbl0_00_31_12_23),
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.RBL1(rbl1_00_31_12_23),
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.WBL(wbl_00_31_12_23),
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.WBLb(~wbl_00_31_12_23)
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);
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// words 32:47
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toysram_32x12 r10 (
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.RWL0({rwl0_32_47_00_11,rwl0_48_31_00_11}),
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.RWL1({rwl1_32_47_00_11,rwl1_48_31_00_11}),
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.WWL({wwl_32_47_00_11,wwl_48_31_00_11}),
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.RBL0(rbl0_32_63_00_11),
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.RBL1(rbl1_32_63_00_11),
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.WBL(wbl_32_63_00_11),
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.WBLb(~wbl_32_63_00_11)
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);
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// words 48:63
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toysram_32x12 r11 (
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.RWL0({rwl0_32_47_12_23,rwl0_48_63_12_23}),
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.RWL1({rwl1_32_47_12_23,rwl1_48_63_12_23}),
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.WWL({wwl_32_47_12_23,wwl_48_63_12_23}),
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.RBL0(rbl0_32_63_12_23),
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.RBL1(rbl1_32_63_12_23),
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.WBL(wbl_32_63_12_23),
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.WBLb(~wbl_32_63_12_23)
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);
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end
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endgenerate
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// word lines
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assign rwl0_00_15_00_11[0] = rd0_c_na0 & rd0_na1_na2 & rd0_na3 & rd0_na4_na5;
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assign rwl1_00_15_00_11[0] = rd1_c_na0 & rd1_na1_na2 & rd1_na3 & rd1_na4_na5;
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assign wwl_00_15_00_11[0] = wr0_c_na0 & wr0_na1_na2 & wr0_na3 & wr0_na4_na5;
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assign rwl0_00_15_00_11[1] = rd0_c_na0 & rd0_na1_na2 & rd0_na3 & rd0_na4_a5;
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assign rwl1_00_15_00_11[1] = rd1_c_na0 & rd1_na1_na2 & rd1_na3 & rd1_na4_a5;
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assign wwl_00_15_00_11[1] = wr0_c_na0 & wr0_na1_na2 & wr0_na3 & wr0_na4_a5;
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assign rwl0_00_15_00_11[2] = rd0_c_na0 & rd0_na1_na2 & rd0_na3 & rd0_a4_na5;
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assign rwl1_00_15_00_11[2] = rd1_c_na0 & rd1_na1_na2 & rd1_na3 & rd1_a4_na5;
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assign wwl_00_15_00_11[2] = wr0_c_na0 & wr0_na1_na2 & wr0_na3 & wr0_a4_na5;
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assign rwl0_00_15_00_11[3] = rd0_c_na0 & rd0_na1_na2 & rd0_na3 & rd0_a4_a5;
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assign rwl1_00_15_00_11[3] = rd1_c_na0 & rd1_na1_na2 & rd1_na3 & rd1_a4_a5;
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assign wwl_00_15_00_11[3] = wr0_c_na0 & wr0_na1_na2 & wr0_na3 & wr0_a4_a5;
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assign rwl0_00_15_00_11[4] = rd0_c_na0 & rd0_na1_na2 & rd0_a3 & rd0_na4_na5;
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assign rwl1_00_15_00_11[4] = rd1_c_na0 & rd1_na1_na2 & rd1_a3 & rd1_na4_na5;
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assign wwl_00_15_00_11[4] = wr0_c_na0 & wr0_na1_na2 & wr0_a3 & wr0_na4_na5;
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assign rwl0_00_15_00_11[5] = rd0_c_na0 & rd0_na1_na2 & rd0_a3 & rd0_na4_a5;
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assign rwl1_00_15_00_11[5] = rd1_c_na0 & rd1_na1_na2 & rd1_a3 & rd1_na4_a5;
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assign wwl_00_15_00_11[5] = wr0_c_na0 & wr0_na1_na2 & wr0_a3 & wr0_na4_a5;
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assign rwl0_00_15_00_11[6] = rd0_c_na0 & rd0_na1_na2 & rd0_a3 & rd0_a4_na5;
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assign rwl1_00_15_00_11[6] = rd1_c_na0 & rd1_na1_na2 & rd1_a3 & rd1_a4_na5;
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assign wwl_00_15_00_11[6] = wr0_c_na0 & wr0_na1_na2 & wr0_a3 & wr0_a4_na5;
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assign rwl0_00_15_00_11[7] = rd0_c_na0 & rd0_na1_na2 & rd0_a3 & rd0_a4_a5;
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assign rwl1_00_15_00_11[7] = rd1_c_na0 & rd1_na1_na2 & rd1_a3 & rd1_a4_a5;
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assign wwl_00_15_00_11[7] = wr0_c_na0 & wr0_na1_na2 & wr0_a3 & wr0_a4_a5;
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assign rwl0_00_15_00_11[8] = rd0_c_na0 & rd0_na1_a2 & rd0_na3 & rd0_na4_na5;
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assign rwl1_00_15_00_11[8] = rd1_c_na0 & rd1_na1_a2 & rd1_na3 & rd1_na4_na5;
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assign wwl_00_15_00_11[8] = wr0_c_na0 & wr0_na1_a2 & wr0_na3 & wr0_na4_na5;
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assign rwl0_00_15_00_11[9] = rd0_c_na0 & rd0_na1_a2 & rd0_na3 & rd0_na4_a5;
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assign rwl1_00_15_00_11[9] = rd1_c_na0 & rd1_na1_a2 & rd1_na3 & rd1_na4_a5;
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assign wwl_00_15_00_11[9] = wr0_c_na0 & wr0_na1_a2 & wr0_na3 & wr0_na4_a5;
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assign rwl0_00_15_00_11[10] = rd0_c_na0 & rd0_na1_a2 & rd0_na3 & rd0_a4_na5;
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assign rwl1_00_15_00_11[10] = rd1_c_na0 & rd1_na1_a2 & rd1_na3 & rd1_a4_na5;
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assign wwl_00_15_00_11[10] = wr0_c_na0 & wr0_na1_a2 & wr0_na3 & wr0_a4_na5;
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assign rwl0_00_15_00_11[11] = rd0_c_na0 & rd0_na1_a2 & rd0_na3 & rd0_a4_a5;
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assign rwl1_00_15_00_11[11] = rd1_c_na0 & rd1_na1_a2 & rd1_na3 & rd1_a4_a5;
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assign wwl_00_15_00_11[11] = wr0_c_na0 & wr0_na1_a2 & wr0_na3 & wr0_a4_a5;
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assign rwl0_00_15_00_11[12] = rd0_c_na0 & rd0_na1_a2 & rd0_a3 & rd0_na4_na5;
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assign rwl1_00_15_00_11[12] = rd1_c_na0 & rd1_na1_a2 & rd1_a3 & rd1_na4_na5;
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assign wwl_00_15_00_11[12] = wr0_c_na0 & wr0_na1_a2 & wr0_a3 & wr0_na4_na5;
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assign rwl0_00_15_00_11[13] = rd0_c_na0 & rd0_na1_a2 & rd0_a3 & rd0_na4_a5;
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assign rwl1_00_15_00_11[13] = rd1_c_na0 & rd1_na1_a2 & rd1_a3 & rd1_na4_a5;
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assign wwl_00_15_00_11[13] = wr0_c_na0 & wr0_na1_a2 & wr0_a3 & wr0_na4_a5;
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assign rwl0_00_15_00_11[14] = rd0_c_na0 & rd0_na1_a2 & rd0_a3 & rd0_a4_na5;
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assign rwl1_00_15_00_11[14] = rd1_c_na0 & rd1_na1_a2 & rd1_a3 & rd1_a4_na5;
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assign wwl_00_15_00_11[14] = wr0_c_na0 & wr0_na1_a2 & wr0_a3 & wr0_a4_na5;
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assign rwl0_00_15_00_11[15] = rd0_c_na0 & rd0_na1_a2 & rd0_a3 & rd0_a4_a5;
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assign rwl1_00_15_00_11[15] = rd1_c_na0 & rd1_na1_a2 & rd1_a3 & rd1_a4_a5;
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assign wwl_00_15_00_11[15] = wr0_c_na0 & wr0_na1_a2 & wr0_a3 & wr0_a4_a5;
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assign rwl0_00_15_12_23 = rwl0_00_15_00_11;
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assign rwl1_00_15_12_23 = rwl1_00_15_00_11;
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assign wwl_00_15_12_23 = wwl_00_15_00_11;
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assign rwl0_16_31_00_11[0] = rd0_c_na0 & rd0_a1_na2 & rd0_na3 & rd0_na4_na5;
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assign rwl1_16_31_00_11[0] = rd1_c_na0 & rd1_a1_na2 & rd1_na3 & rd1_na4_na5;
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assign wwl_16_31_00_11[0] = wr0_c_na0 & wr0_a1_na2 & wr0_na3 & wr0_na4_na5;
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assign rwl0_16_31_00_11[1] = rd0_c_na0 & rd0_a1_na2 & rd0_na3 & rd0_na4_a5;
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assign rwl1_16_31_00_11[1] = rd1_c_na0 & rd1_a1_na2 & rd1_na3 & rd1_na4_a5;
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assign wwl_16_31_00_11[1] = wr0_c_na0 & wr0_a1_na2 & wr0_na3 & wr0_na4_a5;
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assign rwl0_16_31_00_11[2] = rd0_c_na0 & rd0_a1_na2 & rd0_na3 & rd0_a4_na5;
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assign rwl1_16_31_00_11[2] = rd1_c_na0 & rd1_a1_na2 & rd1_na3 & rd1_a4_na5;
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assign wwl_16_31_00_11[2] = wr0_c_na0 & wr0_a1_na2 & wr0_na3 & wr0_a4_na5;
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assign rwl0_16_31_00_11[3] = rd0_c_na0 & rd0_a1_na2 & rd0_na3 & rd0_a4_a5;
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assign rwl1_16_31_00_11[3] = rd1_c_na0 & rd1_a1_na2 & rd1_na3 & rd1_a4_a5;
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assign wwl_16_31_00_11[3] = wr0_c_na0 & wr0_a1_na2 & wr0_na3 & wr0_a4_a5;
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assign rwl0_16_31_00_11[4] = rd0_c_na0 & rd0_a1_na2 & rd0_a3 & rd0_na4_na5;
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assign rwl1_16_31_00_11[4] = rd1_c_na0 & rd1_a1_na2 & rd1_a3 & rd1_na4_na5;
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assign wwl_16_31_00_11[4] = wr0_c_na0 & wr0_a1_na2 & wr0_a3 & wr0_na4_na5;
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assign rwl0_16_31_00_11[5] = rd0_c_na0 & rd0_a1_na2 & rd0_a3 & rd0_na4_a5;
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assign rwl1_16_31_00_11[5] = rd1_c_na0 & rd1_a1_na2 & rd1_a3 & rd1_na4_a5;
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assign wwl_16_31_00_11[5] = wr0_c_na0 & wr0_a1_na2 & wr0_a3 & wr0_na4_a5;
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assign rwl0_16_31_00_11[6] = rd0_c_na0 & rd0_a1_na2 & rd0_a3 & rd0_a4_na5;
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assign rwl1_16_31_00_11[6] = rd1_c_na0 & rd1_a1_na2 & rd1_a3 & rd1_a4_na5;
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assign wwl_16_31_00_11[6] = wr0_c_na0 & wr0_a1_na2 & wr0_a3 & wr0_a4_na5;
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assign rwl0_16_31_00_11[7] = rd0_c_na0 & rd0_a1_na2 & rd0_a3 & rd0_a4_a5;
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assign rwl1_16_31_00_11[7] = rd1_c_na0 & rd1_a1_na2 & rd1_a3 & rd1_a4_a5;
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assign wwl_16_31_00_11[7] = wr0_c_na0 & wr0_a1_na2 & wr0_a3 & wr0_a4_a5;
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assign rwl0_16_31_00_11[8] = rd0_c_na0 & rd0_a1_a2 & rd0_na3 & rd0_na4_na5;
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assign rwl1_16_31_00_11[8] = rd1_c_na0 & rd1_a1_a2 & rd1_na3 & rd1_na4_na5;
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assign wwl_16_31_00_11[8] = wr0_c_na0 & wr0_a1_a2 & wr0_na3 & wr0_na4_na5;
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assign rwl0_16_31_00_11[9] = rd0_c_na0 & rd0_a1_a2 & rd0_na3 & rd0_na4_a5;
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assign rwl1_16_31_00_11[9] = rd1_c_na0 & rd1_a1_a2 & rd1_na3 & rd1_na4_a5;
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assign wwl_16_31_00_11[9] = wr0_c_na0 & wr0_a1_a2 & wr0_na3 & wr0_na4_a5;
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assign rwl0_16_31_00_11[10] = rd0_c_na0 & rd0_a1_a2 & rd0_na3 & rd0_a4_na5;
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assign rwl1_16_31_00_11[10] = rd1_c_na0 & rd1_a1_a2 & rd1_na3 & rd1_a4_na5;
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assign wwl_16_31_00_11[10] = wr0_c_na0 & wr0_a1_a2 & wr0_na3 & wr0_a4_na5;
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assign rwl0_16_31_00_11[11] = rd0_c_na0 & rd0_a1_a2 & rd0_na3 & rd0_a4_a5;
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assign rwl1_16_31_00_11[11] = rd1_c_na0 & rd1_a1_a2 & rd1_na3 & rd1_a4_a5;
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assign wwl_16_31_00_11[11] = wr0_c_na0 & wr0_a1_a2 & wr0_na3 & wr0_a4_a5;
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assign rwl0_16_31_00_11[12] = rd0_c_na0 & rd0_a1_a2 & rd0_a3 & rd0_na4_na5;
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assign rwl1_16_31_00_11[12] = rd1_c_na0 & rd1_a1_a2 & rd1_a3 & rd1_na4_na5;
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assign wwl_16_31_00_11[12] = wr0_c_na0 & wr0_a1_a2 & wr0_a3 & wr0_na4_na5;
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assign rwl0_16_31_00_11[13] = rd0_c_na0 & rd0_a1_a2 & rd0_a3 & rd0_na4_a5;
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assign rwl1_16_31_00_11[13] = rd1_c_na0 & rd1_a1_a2 & rd1_a3 & rd1_na4_a5;
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assign wwl_16_31_00_11[13] = wr0_c_na0 & wr0_a1_a2 & wr0_a3 & wr0_na4_a5;
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assign rwl0_16_31_00_11[14] = rd0_c_na0 & rd0_a1_a2 & rd0_a3 & rd0_a4_na5;
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assign rwl1_16_31_00_11[14] = rd1_c_na0 & rd1_a1_a2 & rd1_a3 & rd1_a4_na5;
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assign wwl_16_31_00_11[14] = wr0_c_na0 & wr0_a1_a2 & wr0_a3 & wr0_a4_na5;
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assign rwl0_16_31_00_11[15] = rd0_c_na0 & rd0_a1_a2 & rd0_a3 & rd0_a4_a5;
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assign rwl1_16_31_00_11[15] = rd1_c_na0 & rd1_a1_a2 & rd1_a3 & rd1_a4_a5;
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assign wwl_16_31_00_11[15] = wr0_c_na0 & wr0_a1_a2 & wr0_a3 & wr0_a4_a5;
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assign rwl0_16_31_12_23 = rwl0_16_31_00_11;
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assign rwl1_16_31_12_23 = rwl1_16_31_00_11;
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assign wwl_16_31_12_23 = wwl_16_31_00_11;
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assign rwl0_32_47_00_11[0] = rd0_c_a0 & rd0_na1_na2 & rd0_na3 & rd0_na4_na5;
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assign rwl1_32_47_00_11[0] = rd1_c_a0 & rd1_na1_na2 & rd1_na3 & rd1_na4_na5;
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assign wwl_32_47_00_11[0] = wr0_c_a0 & wr0_na1_na2 & wr0_na3 & wr0_na4_na5;
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assign rwl0_32_47_00_11[1] = rd0_c_a0 & rd0_na1_na2 & rd0_na3 & rd0_na4_a5;
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assign rwl1_32_47_00_11[1] = rd1_c_a0 & rd1_na1_na2 & rd1_na3 & rd1_na4_a5;
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assign wwl_32_47_00_11[1] = wr0_c_a0 & wr0_na1_na2 & wr0_na3 & wr0_na4_a5;
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assign rwl0_32_47_00_11[2] = rd0_c_a0 & rd0_na1_na2 & rd0_na3 & rd0_a4_na5;
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assign rwl1_32_47_00_11[2] = rd1_c_a0 & rd1_na1_na2 & rd1_na3 & rd1_a4_na5;
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assign wwl_32_47_00_11[2] = wr0_c_a0 & wr0_na1_na2 & wr0_na3 & wr0_a4_na5;
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assign rwl0_32_47_00_11[3] = rd0_c_a0 & rd0_na1_na2 & rd0_na3 & rd0_a4_a5;
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assign rwl1_32_47_00_11[3] = rd1_c_a0 & rd1_na1_na2 & rd1_na3 & rd1_a4_a5;
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assign wwl_32_47_00_11[3] = wr0_c_a0 & wr0_na1_na2 & wr0_na3 & wr0_a4_a5;
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assign rwl0_32_47_00_11[4] = rd0_c_a0 & rd0_na1_na2 & rd0_a3 & rd0_na4_na5;
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assign rwl1_32_47_00_11[4] = rd1_c_a0 & rd1_na1_na2 & rd1_a3 & rd1_na4_na5;
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assign wwl_32_47_00_11[4] = wr0_c_a0 & wr0_na1_na2 & wr0_a3 & wr0_na4_na5;
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assign rwl0_32_47_00_11[5] = rd0_c_a0 & rd0_na1_na2 & rd0_a3 & rd0_na4_a5;
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assign rwl1_32_47_00_11[5] = rd1_c_a0 & rd1_na1_na2 & rd1_a3 & rd1_na4_a5;
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assign wwl_32_47_00_11[5] = wr0_c_a0 & wr0_na1_na2 & wr0_a3 & wr0_na4_a5;
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assign rwl0_32_47_00_11[6] = rd0_c_a0 & rd0_na1_na2 & rd0_a3 & rd0_a4_na5;
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assign rwl1_32_47_00_11[6] = rd1_c_a0 & rd1_na1_na2 & rd1_a3 & rd1_a4_na5;
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assign wwl_32_47_00_11[6] = wr0_c_a0 & wr0_na1_na2 & wr0_a3 & wr0_a4_na5;
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assign rwl0_32_47_00_11[7] = rd0_c_a0 & rd0_na1_na2 & rd0_a3 & rd0_a4_a5;
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assign rwl1_32_47_00_11[7] = rd1_c_a0 & rd1_na1_na2 & rd1_a3 & rd1_a4_a5;
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assign wwl_32_47_00_11[7] = wr0_c_a0 & wr0_na1_na2 & wr0_a3 & wr0_a4_a5;
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assign rwl0_32_47_00_11[8] = rd0_c_a0 & rd0_na1_a2 & rd0_na3 & rd0_na4_na5;
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assign rwl1_32_47_00_11[8] = rd1_c_a0 & rd1_na1_a2 & rd1_na3 & rd1_na4_na5;
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assign wwl_32_47_00_11[8] = wr0_c_a0 & wr0_na1_a2 & wr0_na3 & wr0_na4_na5;
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assign rwl0_32_47_00_11[9] = rd0_c_a0 & rd0_na1_a2 & rd0_na3 & rd0_na4_a5;
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assign rwl1_32_47_00_11[9] = rd1_c_a0 & rd1_na1_a2 & rd1_na3 & rd1_na4_a5;
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assign wwl_32_47_00_11[9] = wr0_c_a0 & wr0_na1_a2 & wr0_na3 & wr0_na4_a5;
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assign rwl0_32_47_00_11[10] = rd0_c_a0 & rd0_na1_a2 & rd0_na3 & rd0_a4_na5;
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assign rwl1_32_47_00_11[10] = rd1_c_a0 & rd1_na1_a2 & rd1_na3 & rd1_a4_na5;
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assign wwl_32_47_00_11[10] = wr0_c_a0 & wr0_na1_a2 & wr0_na3 & wr0_a4_na5;
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assign rwl0_32_47_00_11[11] = rd0_c_a0 & rd0_na1_a2 & rd0_na3 & rd0_a4_a5;
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assign rwl1_32_47_00_11[11] = rd1_c_a0 & rd1_na1_a2 & rd1_na3 & rd1_a4_a5;
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assign wwl_32_47_00_11[11] = wr0_c_a0 & wr0_na1_a2 & wr0_na3 & wr0_a4_a5;
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assign rwl0_32_47_00_11[12] = rd0_c_a0 & rd0_na1_a2 & rd0_a3 & rd0_na4_na5;
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assign rwl1_32_47_00_11[12] = rd1_c_a0 & rd1_na1_a2 & rd1_a3 & rd1_na4_na5;
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assign wwl_32_47_00_11[12] = wr0_c_a0 & wr0_na1_a2 & wr0_a3 & wr0_na4_na5;
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assign rwl0_32_47_00_11[13] = rd0_c_a0 & rd0_na1_a2 & rd0_a3 & rd0_na4_a5;
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assign rwl1_32_47_00_11[13] = rd1_c_a0 & rd1_na1_a2 & rd1_a3 & rd1_na4_a5;
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assign wwl_32_47_00_11[13] = wr0_c_a0 & wr0_na1_a2 & wr0_a3 & wr0_na4_a5;
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assign rwl0_32_47_00_11[14] = rd0_c_a0 & rd0_na1_a2 & rd0_a3 & rd0_a4_na5;
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assign rwl1_32_47_00_11[14] = rd1_c_a0 & rd1_na1_a2 & rd1_a3 & rd1_a4_na5;
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assign wwl_32_47_00_11[14] = wr0_c_a0 & wr0_na1_a2 & wr0_a3 & wr0_a4_na5;
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assign rwl0_32_47_00_11[15] = rd0_c_a0 & rd0_na1_a2 & rd0_a3 & rd0_a4_a5;
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assign rwl1_32_47_00_11[15] = rd1_c_a0 & rd1_na1_a2 & rd1_a3 & rd1_a4_a5;
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assign wwl_32_47_00_11[15] = wr0_c_a0 & wr0_na1_a2 & wr0_a3 & wr0_a4_a5;
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assign rwl0_32_47_12_23 = rwl0_32_47_00_11;
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assign rwl1_32_47_12_23 = rwl1_32_47_00_11;
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assign wwl_32_47_12_23 = wwl_32_47_00_11;
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assign rwl0_48_63_00_11[0] = rd0_c_a0 & rd0_a1_na2 & rd0_na3 & rd0_na4_na5;
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assign rwl1_48_63_00_11[0] = rd1_c_a0 & rd1_a1_na2 & rd1_na3 & rd1_na4_na5;
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assign wwl_48_63_00_11[0] = wr0_c_a0 & wr0_a1_na2 & wr0_na3 & wr0_na4_na5;
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assign rwl0_48_63_00_11[1] = rd0_c_a0 & rd0_a1_na2 & rd0_na3 & rd0_na4_a5;
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assign rwl1_48_63_00_11[1] = rd1_c_a0 & rd1_a1_na2 & rd1_na3 & rd1_na4_a5;
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assign wwl_48_63_00_11[1] = wr0_c_a0 & wr0_a1_na2 & wr0_na3 & wr0_na4_a5;
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assign rwl0_48_63_00_11[2] = rd0_c_a0 & rd0_a1_na2 & rd0_na3 & rd0_a4_na5;
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assign rwl1_48_63_00_11[2] = rd1_c_a0 & rd1_a1_na2 & rd1_na3 & rd1_a4_na5;
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assign wwl_48_63_00_11[2] = wr0_c_a0 & wr0_a1_na2 & wr0_na3 & wr0_a4_na5;
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assign rwl0_48_63_00_11[3] = rd0_c_a0 & rd0_a1_na2 & rd0_na3 & rd0_a4_a5;
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assign rwl1_48_63_00_11[3] = rd1_c_a0 & rd1_a1_na2 & rd1_na3 & rd1_a4_a5;
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assign wwl_48_63_00_11[3] = wr0_c_a0 & wr0_a1_na2 & wr0_na3 & wr0_a4_a5;
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assign rwl0_48_63_00_11[4] = rd0_c_a0 & rd0_a1_na2 & rd0_a3 & rd0_na4_na5;
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assign rwl1_48_63_00_11[4] = rd1_c_a0 & rd1_a1_na2 & rd1_a3 & rd1_na4_na5;
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assign wwl_48_63_00_11[4] = wr0_c_a0 & wr0_a1_na2 & wr0_a3 & wr0_na4_na5;
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assign rwl0_48_63_00_11[5] = rd0_c_a0 & rd0_a1_na2 & rd0_a3 & rd0_na4_a5;
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assign rwl1_48_63_00_11[5] = rd1_c_a0 & rd1_a1_na2 & rd1_a3 & rd1_na4_a5;
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assign wwl_48_63_00_11[5] = wr0_c_a0 & wr0_a1_na2 & wr0_a3 & wr0_na4_a5;
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assign rwl0_48_63_00_11[6] = rd0_c_a0 & rd0_a1_na2 & rd0_a3 & rd0_a4_na5;
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assign rwl1_48_63_00_11[6] = rd1_c_a0 & rd1_a1_na2 & rd1_a3 & rd1_a4_na5;
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assign wwl_48_63_00_11[6] = wr0_c_a0 & wr0_a1_na2 & wr0_a3 & wr0_a4_na5;
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assign rwl0_48_63_00_11[7] = rd0_c_a0 & rd0_a1_na2 & rd0_a3 & rd0_a4_a5;
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assign rwl1_48_63_00_11[7] = rd1_c_a0 & rd1_a1_na2 & rd1_a3 & rd1_a4_a5;
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assign wwl_48_63_00_11[7] = wr0_c_a0 & wr0_a1_na2 & wr0_a3 & wr0_a4_a5;
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assign rwl0_48_63_00_11[8] = rd0_c_a0 & rd0_a1_a2 & rd0_na3 & rd0_na4_na5;
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assign rwl1_48_63_00_11[8] = rd1_c_a0 & rd1_a1_a2 & rd1_na3 & rd1_na4_na5;
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assign wwl_48_63_00_11[8] = wr0_c_a0 & wr0_a1_a2 & wr0_na3 & wr0_na4_na5;
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assign rwl0_48_63_00_11[9] = rd0_c_a0 & rd0_a1_a2 & rd0_na3 & rd0_na4_a5;
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assign rwl1_48_63_00_11[9] = rd1_c_a0 & rd1_a1_a2 & rd1_na3 & rd1_na4_a5;
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assign wwl_48_63_00_11[9] = wr0_c_a0 & wr0_a1_a2 & wr0_na3 & wr0_na4_a5;
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assign rwl0_48_63_00_11[10] = rd0_c_a0 & rd0_a1_a2 & rd0_na3 & rd0_a4_na5;
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assign rwl1_48_63_00_11[10] = rd1_c_a0 & rd1_a1_a2 & rd1_na3 & rd1_a4_na5;
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assign wwl_48_63_00_11[10] = wr0_c_a0 & wr0_a1_a2 & wr0_na3 & wr0_a4_na5;
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assign rwl0_48_63_00_11[11] = rd0_c_a0 & rd0_a1_a2 & rd0_na3 & rd0_a4_a5;
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assign rwl1_48_63_00_11[11] = rd1_c_a0 & rd1_a1_a2 & rd1_na3 & rd1_a4_a5;
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assign wwl_48_63_00_11[11] = wr0_c_a0 & wr0_a1_a2 & wr0_na3 & wr0_a4_a5;
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assign rwl0_48_63_00_11[12] = rd0_c_a0 & rd0_a1_a2 & rd0_a3 & rd0_na4_na5;
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assign rwl1_48_63_00_11[12] = rd1_c_a0 & rd1_a1_a2 & rd1_a3 & rd1_na4_na5;
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assign wwl_48_63_00_11[12] = wr0_c_a0 & wr0_a1_a2 & wr0_a3 & wr0_na4_na5;
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assign rwl0_48_63_00_11[13] = rd0_c_a0 & rd0_a1_a2 & rd0_a3 & rd0_na4_a5;
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assign rwl1_48_63_00_11[13] = rd1_c_a0 & rd1_a1_a2 & rd1_a3 & rd1_na4_a5;
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assign wwl_48_63_00_11[13] = wr0_c_a0 & wr0_a1_a2 & wr0_a3 & wr0_na4_a5;
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assign rwl0_48_63_00_11[14] = rd0_c_a0 & rd0_a1_a2 & rd0_a3 & rd0_a4_na5;
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assign rwl1_48_63_00_11[14] = rd1_c_a0 & rd1_a1_a2 & rd1_a3 & rd1_a4_na5;
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assign wwl_48_63_00_11[14] = wr0_c_a0 & wr0_a1_a2 & wr0_a3 & wr0_a4_na5;
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assign rwl0_48_63_00_11[15] = rd0_c_a0 & rd0_a1_a2 & rd0_a3 & rd0_a4_a5;
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assign rwl1_48_63_00_11[15] = rd1_c_a0 & rd1_a1_a2 & rd1_a3 & rd1_a4_a5;
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assign wwl_48_63_00_11[15] = wr0_c_a0 & wr0_a1_a2 & wr0_a3 & wr0_a4_a5;
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assign rwl0_48_63_12_23 = rwl0_48_63_00_11;
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assign rwl1_48_63_12_23 = rwl1_48_63_00_11;
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assign wwl_48_63_12_23 = wwl_48_63_00_11;
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// bit lines
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genvar i;
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generate
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for (i = 0; i < 12; i = i + 1) begin
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assign rd0_dat[i] = (~rbl0_00_15_00_11[i]) | (~rbl0_16_31_00_11[i]) | (~rbl0_32_47_00_11[i]) | (~rbl0_48_63_00_11[i]);
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assign rd1_dat[i] = (~rbl1_00_15_00_11[i]) | (~rbl1_16_31_00_11[i]) | (~rbl1_32_47_00_11[i]) | (~rbl1_48_63_00_11[i]);
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end
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for (i = 0; i < 12; i = i + 1) begin
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assign rd0_dat[i+12] = (~rbl0_00_15_12_23[i]) | (~rbl0_16_31_12_23[i]) | (~rbl0_32_47_12_23[i]) | (~rbl0_48_63_12_23[i]);
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assign rd1_dat[i+12] = (~rbl1_00_15_12_23[i]) | (~rbl1_16_31_12_23[i]) | (~rbl1_32_47_12_23[i]) | (~rbl1_48_63_12_23[i]);
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end
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endgenerate
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assign wbl_00_15_00_11 = wr0_dat[0:11];
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assign wbl_00_15_12_23 = wr0_dat[12:23];
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assign wbl_16_31_00_11 = wr0_dat[0:11];
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assign wbl_16_31_12_23 = wr0_dat[12:23];
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assign wbl_32_47_00_11 = wr0_dat[0:11];
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assign wbl_32_47_12_23 = wr0_dat[12:23];
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assign wbl_48_63_00_11 = wr0_dat[0:11];
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assign wbl_48_63_12_23 = wr0_dat[12:23];
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endmodule
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