sim 64x72

master
openpowerwtf 1 year ago
parent 1791868f4d
commit 3ae2375de3

@ -8,7 +8,7 @@

#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM

SIM_BUILD ?= build_32x32
#SIM_BUILD ?= build
SIM ?= icarus

# options
@ -17,9 +17,9 @@ SIM ?= icarus
#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM

# icarus

VERILOG_ROOT = src

#
#VERILOG_ROOT = ../src/array_behav
VERILOG_ROOT = src/array_shard
COMPILE_ARGS = -I$(VERILOG_ROOT) -y$(VERILOG_ROOT)

# other options
@ -27,12 +27,12 @@ COMPILE_ARGS = -I$(VERILOG_ROOT) -y$(VERILOG_ROOT)
# rtl
TOPLEVEL_LANG = verilog
# top-level to enable trace, etc.
VERILOG_SOURCES = ./test_ra_sdr_32x32.v
TOPLEVEL = test_ra_sdr_32x32
VERILOG_SOURCES = ./tb_ra_64x72_2r1w.v
TOPLEVEL = tb_ra_64x72_2r1w

# python test
MODULE = tb
TESTCASE = tb_32x32
MODULE = tb_ra_64x72
TESTCASE = tb

# cocotb make rules
include $(shell cocotb-config --makefiles)/Makefile.sim
@ -42,5 +42,5 @@ build: clean sim fst
run: sim fst

fst:
vcd2fst test_ra_sdr_32x32.vcd test_ra_sdr_32x32.fst
#rm test_ra_sdr_32x32.vcd
vcd2fst tb_ra_64x72.vcd tb_ra_64x72.fst
rm tb_ra_64x72.vcd

File diff suppressed because it is too large Load Diff

@ -0,0 +1,82 @@
[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Tue Nov 8 18:51:49 2022
[*]
[dumpfile] "/data/projects/toy-sram/rtl/sim/coco/tb_ra_64x72.fst"
[dumpfile_mtime] "Tue Nov 8 18:34:46 2022"
[dumpfile_size] 12534
[savefile] "/data/projects/toy-sram/rtl/sim/coco/ra_64x72_2r1w.gtkw"
[timestart] 23310
[size] 1699 1047
[pos] 192 243
*-12.000000 28000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ra_64x72_2r1w.
[treeopen] tb_ra_64x72_2r1w.ra.
[treeopen] tb_ra_64x72_2r1w.ra.ra0.
[sst_width] 218
[signals_width] 257
[sst_expanded] 1
[sst_vpaned_height] 301
@28
tb_ra_64x72_2r1w.clk
tb_ra_64x72_2r1w.rd_enb_0
@22
tb_ra_64x72_2r1w.rd_adr_0[0:5]
tb_ra_64x72_2r1w.rd_dat_0[0:71]
@28
tb_ra_64x72_2r1w.rd_enb_1
@22
tb_ra_64x72_2r1w.rd_adr_1[0:5]
tb_ra_64x72_2r1w.rd_dat_1[0:71]
@28
tb_ra_64x72_2r1w.wr_enb_0
@22
tb_ra_64x72_2r1w.wr_adr_0[0:5]
tb_ra_64x72_2r1w.wr_dat_0[0:71]
@200
-RA
@28
tb_ra_64x72_2r1w.ra.rd_enb_0_q
@22
tb_ra_64x72_2r1w.ra.rd_adr_0_q[0:5]
tb_ra_64x72_2r1w.ra.rd_dat_0_q[0:71]
@28
tb_ra_64x72_2r1w.ra.rd_enb_1_q
@22
tb_ra_64x72_2r1w.ra.rd_adr_1_q[0:5]
tb_ra_64x72_2r1w.ra.rd_dat_1_q[0:71]
@28
tb_ra_64x72_2r1w.ra.wr_enb_0_q
@22
tb_ra_64x72_2r1w.ra.wr_adr_0_q[0:5]
tb_ra_64x72_2r1w.ra.wr_dat_0_q[0:71]
@200
-RA0
-W0x
@22
tb_ra_64x72_2r1w.ra.ra0.w00.mem_00[0:11]
tb_ra_64x72_2r1w.ra.ra0.w00.mem_01[0:11]
tb_ra_64x72_2r1w.ra.ra0.w00.mem_02[0:11]
tb_ra_64x72_2r1w.ra.ra0.w00.mem_03[0:11]
tb_ra_64x72_2r1w.ra.ra0.w01.mem_00[0:11]
tb_ra_64x72_2r1w.ra.ra0.w01.mem_01[0:11]
tb_ra_64x72_2r1w.ra.ra0.w01.mem_02[0:11]
@23
tb_ra_64x72_2r1w.ra.ra0.w01.mem_03[0:11]
@22
tb_ra_64x72_2r1w.ra.ra0.w00.RWL0[0:15]
tb_ra_64x72_2r1w.ra.ra0.w00.RWL1[0:15]
tb_ra_64x72_2r1w.ra.ra0.w00.RBL0[0:11]
tb_ra_64x72_2r1w.ra.ra0.w00.RBL1[0:11]
tb_ra_64x72_2r1w.ra.ra0.w00.WWL[0:15]
tb_ra_64x72_2r1w.ra.ra0.w01.RWL0[0:15]
tb_ra_64x72_2r1w.ra.ra0.w01.RWL1[0:15]
tb_ra_64x72_2r1w.ra.ra0.w01.RBL0[0:11]
tb_ra_64x72_2r1w.ra.ra0.w01.RBL1[0:11]
tb_ra_64x72_2r1w.ra.ra0.w01.WWL[0:15]
tb_ra_64x72_2r1w.ra.ra0.w00.mem_08[0:11]
tb_ra_64x72_2r1w.ra.ra0.w01.mem_08[0:11]
tb_ra_64x72_2r1w.ra.ra0.w00.WWL[0:15]
tb_ra_64x72_2r1w.ra.ra0.w01.WWL[0:15]
[pattern_trace] 1
[pattern_trace] 0

@ -1,174 +1,165 @@
# Cocotb + Icarus Verilog Array Sim

Cocotb test created from original pyverilator version - run random commands using 64x72 logical array.

## Array Wrapper

* two versions
* Makefile_64x72 (behavioral-only)
* Makefile_64x72_shard (behavioral, netlist-style RTL)

* compile and run

```
make -f Makefile_sdr_32x32 build

make RANDOM_SEED=8675309 -f Makefile_64x72_shard build
gtkwave tb_ra_64x72.fst ra_64x72_2r1w.gtkw
```

* just run (tb.py changes, etc.)
* just run

```
make -f Makefile_sdr_32x32 run

make -f Makefile_64x72_shard
```

* results

```
make -f Makefile_sdr_32x32 run >& sim_32x32.txt

MODULE=tb TESTCASE=tb_32x32 TOPLEVEL=test_ra_sdr_32x32 TOPLEVEL_LANG=verilog \
/usr/local/bin/vvp -M /home/wtf/.local/lib/python3.8/site-packages/cocotb/libs -m libcocotbvpi_icarus build_32x32/sim.vvp
-.--ns INFO cocotb.gpi ..mbed/gpi_embed.cpp:76 in set_program_name_in_venv Did not detect Python virtual environment. Using system-wide Python interpreter
-.--ns INFO cocotb.gpi ../gpi/GpiCommon.cpp:99 in gpi_print_registered_impl VPI registered
0.00ns INFO Running on Icarus Verilog version 12.0 (devel)
0.00ns INFO Running tests with cocotb v1.7.0.dev0 from /home/wtf/.local/lib/python3.8/site-packages/cocotb
0.00ns INFO Seeding Python random module with 1654704020
0.00ns INFO Found test tb.tb_32x32
0.00ns INFO running tb_32x32 (1/0)
ToySRAM 32x32 array test
0.00ns INFO [00000001] [00000001] Resetting...
9.00ns INFO [00000010] [00000010] Releasing reset.
25.00ns INFO [00000027] Initializing array...
25.00ns INFO [00000027] Port=0 WR @00=00555500
26.00ns INFO [00000028] Port=0 WR @01=01555501
27.00ns INFO [00000029] Port=0 WR @02=02555502
28.00ns INFO [00000030] Port=0 WR @03=03555503
29.00ns INFO [00000031] Port=0 WR @04=04555504
30.00ns INFO [00000032] Port=0 WR @05=05555505
31.00ns INFO [00000033] Port=0 WR @06=06555506
32.00ns INFO [00000034] Port=0 WR @07=07555507
33.00ns INFO [00000035] Port=0 WR @08=08555508
MODULE=tb_ra_64x72 TESTCASE=tb TOPLEVEL=tb_ra_64x72_2r1w TOPLEVEL_LANG=verilog \
/usr/local/bin/vvp -M /home/wtf/.local/lib/python3.10/site-packages/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp
-.--ns INFO gpi ..mbed/gpi_embed.cpp:76 in set_program_name_in_venv Did not detect Python virtual environment. Using system-wide Python interpreter
-.--ns INFO gpi ../gpi/GpiCommon.cpp:101 in gpi_print_registered_impl VPI registered
0.00ns INFO cocotb Running on Icarus Verilog version 12.0 (devel)
0.00ns INFO cocotb Running tests with cocotb v1.7.1 from /home/wtf/.local/lib/python3.10/site-packages/cocotb
0.00ns INFO cocotb Seeding Python random module with supplied seed 8675309
0.00ns INFO cocotb.regression Found test tb_ra_64x72.tb
0.00ns INFO cocotb.regression running tb (1/1)
ToySRAM 64x72 array test
0.00ns INFO cocotb.tb_ra_64x72_2r1w [00000001] Resetting...
9.00ns INFO cocotb.tb_ra_64x72_2r1w [00000010] Releasing reset.
25.00ns INFO cocotb.tb_ra_64x72_2r1w [00000027] Initializing array...
25.00ns INFO cocotb.tb_ra_64x72_2r1w [00000027] Port=0 WR @00=005555555555555500
26.00ns INFO cocotb.tb_ra_64x72_2r1w [00000028] Port=0 WR @01=015555555555555501
27.00ns INFO cocotb.tb_ra_64x72_2r1w [00000029] Port=0 WR @02=025555555555555502
28.00ns INFO cocotb.tb_ra_64x72_2r1w [00000030] Port=0 WR @03=035555555555555503
29.00ns INFO cocotb.tb_ra_64x72_2r1w [00000031] Port=0 WR @04=045555555555555504
30.00ns INFO cocotb.tb_ra_64x72_2r1w [00000032] Port=0 WR @05=055555555555555505
31.00ns INFO cocotb.tb_ra_64x72_2r1w [00000033] Port=0 WR @06=065555555555555506
32.00ns INFO cocotb.tb_ra_64x72_2r1w [00000034] Port=0 WR @07=075555555555555507
33.00ns INFO cocotb.tb_ra_64x72_2r1w [00000035] Port=0 WR @08=085555555555555508
34.00ns INFO cocotb.tb_ra_64x72_2r1w [00000036] Port=0 WR @09=095555555555555509
35.00ns INFO cocotb.tb_ra_64x72_2r1w [00000037] Port=0 WR @0A=0A555555555555550A
36.00ns INFO cocotb.tb_ra_64x72_2r1w [00000038] Port=0 WR @0B=0B555555555555550B
37.00ns INFO cocotb.tb_ra_64x72_2r1w [00000039] Port=0 WR @0C=0C555555555555550C
38.00ns INFO cocotb.tb_ra_64x72_2r1w [00000040] Port=0 WR @0D=0D555555555555550D
39.00ns INFO cocotb.tb_ra_64x72_2r1w [00000041] Port=0 WR @0E=0E555555555555550E
40.00ns INFO cocotb.tb_ra_64x72_2r1w [00000042] Port=0 WR @0F=0F555555555555550F
41.00ns INFO cocotb.tb_ra_64x72_2r1w [00000043] Port=0 WR @10=105555555555555510
42.00ns INFO cocotb.tb_ra_64x72_2r1w [00000044] Port=0 WR @11=115555555555555511
43.00ns INFO cocotb.tb_ra_64x72_2r1w [00000045] Port=0 WR @12=125555555555555512
44.00ns INFO cocotb.tb_ra_64x72_2r1w [00000046] Port=0 WR @13=135555555555555513
45.00ns INFO cocotb.tb_ra_64x72_2r1w [00000047] Port=0 WR @14=145555555555555514
46.00ns INFO cocotb.tb_ra_64x72_2r1w [00000048] Port=0 WR @15=155555555555555515
47.00ns INFO cocotb.tb_ra_64x72_2r1w [00000049] Port=0 WR @16=165555555555555516
48.00ns INFO cocotb.tb_ra_64x72_2r1w [00000050] Port=0 WR @17=175555555555555517
49.00ns INFO cocotb.tb_ra_64x72_2r1w [00000051] Port=0 WR @18=185555555555555518
50.00ns INFO cocotb.tb_ra_64x72_2r1w [00000052] Port=0 WR @19=195555555555555519
51.00ns INFO cocotb.tb_ra_64x72_2r1w [00000053] Port=0 WR @1A=1A555555555555551A
52.00ns INFO cocotb.tb_ra_64x72_2r1w [00000054] Port=0 WR @1B=1B555555555555551B
53.00ns INFO cocotb.tb_ra_64x72_2r1w [00000055] Port=0 WR @1C=1C555555555555551C
54.00ns INFO cocotb.tb_ra_64x72_2r1w [00000056] Port=0 WR @1D=1D555555555555551D
55.00ns INFO cocotb.tb_ra_64x72_2r1w [00000057] Port=0 WR @1E=1E555555555555551E
56.00ns INFO cocotb.tb_ra_64x72_2r1w [00000058] Port=0 WR @1F=1F555555555555551F
57.00ns INFO cocotb.tb_ra_64x72_2r1w [00000059] Port=0 WR @20=205555555555555520
58.00ns INFO cocotb.tb_ra_64x72_2r1w [00000060] Port=0 WR @21=215555555555555521
59.00ns INFO cocotb.tb_ra_64x72_2r1w [00000061] Port=0 WR @22=225555555555555522
60.00ns INFO cocotb.tb_ra_64x72_2r1w [00000062] Port=0 WR @23=235555555555555523
61.00ns INFO cocotb.tb_ra_64x72_2r1w [00000063] Port=0 WR @24=245555555555555524
62.00ns INFO cocotb.tb_ra_64x72_2r1w [00000064] Port=0 WR @25=255555555555555525
63.00ns INFO cocotb.tb_ra_64x72_2r1w [00000065] Port=0 WR @26=265555555555555526
64.00ns INFO cocotb.tb_ra_64x72_2r1w [00000066] Port=0 WR @27=275555555555555527
65.00ns INFO cocotb.tb_ra_64x72_2r1w [00000067] Port=0 WR @28=285555555555555528
66.00ns INFO cocotb.tb_ra_64x72_2r1w [00000068] Port=0 WR @29=295555555555555529
67.00ns INFO cocotb.tb_ra_64x72_2r1w [00000069] Port=0 WR @2A=2A555555555555552A
68.00ns INFO cocotb.tb_ra_64x72_2r1w [00000070] Port=0 WR @2B=2B555555555555552B
69.00ns INFO cocotb.tb_ra_64x72_2r1w [00000071] Port=0 WR @2C=2C555555555555552C
70.00ns INFO cocotb.tb_ra_64x72_2r1w [00000072] Port=0 WR @2D=2D555555555555552D
71.00ns INFO cocotb.tb_ra_64x72_2r1w [00000073] Port=0 WR @2E=2E555555555555552E
72.00ns INFO cocotb.tb_ra_64x72_2r1w [00000074] Port=0 WR @2F=2F555555555555552F
73.00ns INFO cocotb.tb_ra_64x72_2r1w [00000075] Port=0 WR @30=305555555555555530
74.00ns INFO cocotb.tb_ra_64x72_2r1w [00000076] Port=0 WR @31=315555555555555531
75.00ns INFO cocotb.tb_ra_64x72_2r1w [00000077] Port=0 WR @32=325555555555555532
76.00ns INFO cocotb.tb_ra_64x72_2r1w [00000078] Port=0 WR @33=335555555555555533
77.00ns INFO cocotb.tb_ra_64x72_2r1w [00000079] Port=0 WR @34=345555555555555534
78.00ns INFO cocotb.tb_ra_64x72_2r1w [00000080] Port=0 WR @35=355555555555555535
79.00ns INFO cocotb.tb_ra_64x72_2r1w [00000081] Port=0 WR @36=365555555555555536
80.00ns INFO cocotb.tb_ra_64x72_2r1w [00000082] Port=0 WR @37=375555555555555537
81.00ns INFO cocotb.tb_ra_64x72_2r1w [00000083] Port=0 WR @38=385555555555555538
82.00ns INFO cocotb.tb_ra_64x72_2r1w [00000084] Port=0 WR @39=395555555555555539
83.00ns INFO cocotb.tb_ra_64x72_2r1w [00000085] Port=0 WR @3A=3A555555555555553A
84.00ns INFO cocotb.tb_ra_64x72_2r1w [00000086] Port=0 WR @3B=3B555555555555553B
85.00ns INFO cocotb.tb_ra_64x72_2r1w [00000087] Port=0 WR @3C=3C555555555555553C
86.00ns INFO cocotb.tb_ra_64x72_2r1w [00000088] Port=0 WR @3D=3D555555555555553D
87.00ns INFO cocotb.tb_ra_64x72_2r1w [00000089] Port=0 WR @3E=3E555555555555553E
88.00ns INFO cocotb.tb_ra_64x72_2r1w [00000090] Port=0 WR @3F=3F555555555555553F
89.00ns INFO cocotb.tb_ra_64x72_2r1w [00000091] Running random commands...
89.50ns INFO cocotb.tb_ra_64x72_2r1w [00000091] Port=0 WR @29=9BFB82E63586CCC8C7
90.50ns INFO cocotb.tb_ra_64x72_2r1w [00000092] Port=0 WR @1C=23C37F63E32FE18FAE
90.50ns INFO cocotb.tb_ra_64x72_2r1w [00000092] Port=0 RD @0D
91.50ns INFO cocotb.tb_ra_64x72_2r1w [00000093] Port=0 RD @1E
91.50ns INFO cocotb.tb_ra_64x72_2r1w [00000093] Port=1 RD @05
92.50ns INFO cocotb.tb_ra_64x72_2r1w [00000094] * RD COMPARE * port=0 adr=0D act=0D555555555555550D exp=0D555555555555550D
92.50ns INFO cocotb.tb_ra_64x72_2r1w [00000094] Port=0 RD @32
93.50ns INFO cocotb.tb_ra_64x72_2r1w [00000095] * RD COMPARE * port=0 adr=1E act=1E555555555555551E exp=1E555555555555551E
93.50ns INFO cocotb.tb_ra_64x72_2r1w [00000095] * RD COMPARE * port=1 adr=05 act=055555555555555505 exp=055555555555555505
93.50ns INFO cocotb.tb_ra_64x72_2r1w [00000095] Port=0 WR @0F=AC194AC63383A4B51D
94.50ns INFO cocotb.tb_ra_64x72_2r1w [00000096] * RD COMPARE * port=0 adr=32 act=325555555555555532 exp=325555555555555532
95.50ns INFO cocotb.tb_ra_64x72_2r1w [00000097] Port=1 RD @0C
96.50ns INFO cocotb.tb_ra_64x72_2r1w [00000098] Port=0 WR @34=84DC7761056CBA5416
96.50ns INFO cocotb.tb_ra_64x72_2r1w [00000098] Port=0 RD @2C
96.50ns INFO cocotb.tb_ra_64x72_2r1w [00000098] Port=1 RD @0A
97.50ns INFO cocotb.tb_ra_64x72_2r1w [00000099] * RD COMPARE * port=1 adr=0C act=0C555555555555550C exp=0C555555555555550C
97.50ns INFO cocotb.tb_ra_64x72_2r1w [00000099] Port=0 WR @35=C827951DD9AF778AA6
98.00ns INFO cocotb.tb_ra_64x72_2r1w [00000100] ...tick...
...
10037.50ns INFO [00010039] Port=0 WR @12=6C6FD11E
10038.50ns INFO [00010040] Port=0 WR @17=545B517F
10039.50ns INFO [00010041] Port=0 RD @08
10039.50ns INFO [00010041] Port=1 RD @0E
10041.50ns INFO [00010043] * RD COMPARE * port=0 adr=08 act=BE99B13E exp=BE99B13E
10041.50ns INFO [00010043] * RD COMPARE * port=1 adr=0E act=97A2D496 exp=97A2D496
10041.50ns INFO [00010043] Port=0 WR @1A=76434F37
10041.50ns INFO [00010043] Port=1 RD @0D
10042.50ns INFO [00010044] Port=0 WR @12=069ECCCE
10042.50ns INFO [00010044] Port=0 RD @13
10043.50ns INFO [00010045] * RD COMPARE * port=1 adr=0D act=C1C0D7D8 exp=C1C0D7D8
10043.50ns INFO [00010045] Port=0 WR @05=58E318E7
10043.50ns INFO [00010045] Port=0 RD @10
10043.50ns INFO [00010045] Port=1 RD @00
10044.50ns INFO [00010046] * RD COMPARE * port=0 adr=13 act=1D975E90 exp=1D975E90
10044.50ns INFO [00010046] Port=0 RD @14
10044.50ns INFO [00010046] Port=1 RD @1D
10045.50ns INFO [00010047] * RD COMPARE * port=0 adr=10 act=F82AB140 exp=F82AB140
10045.50ns INFO [00010047] * RD COMPARE * port=1 adr=00 act=3C2E724D exp=3C2E724D
10046.50ns INFO [00010048] * RD COMPARE * port=0 adr=14 act=1A27AA07 exp=1A27AA07
10046.50ns INFO [00010048] * RD COMPARE * port=1 adr=1D act=5B9AE71C exp=5B9AE71C
10047.50ns INFO [00010049] Quiescing...
10057.00ns INFO [00010059] Done.
10057.00ns INFO [00010059] Final State

Reads Port 0: 4005
Reads Port 1: 4052
Writes Port 0: 4055
10057.00ns INFO [00010059] [00010059] You has opulence.
10057.00ns INFO tb_32x32 passed
10057.00ns INFO **************************************************************************************
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
**************************************************************************************
** tb.tb_32x32 PASS 10057.00 8.54 1177.70 **
**************************************************************************************
** TESTS=0 PASS=1 FAIL=0 SKIP=0 10057.00 8.56 1174.42 **
**************************************************************************************

VCD info: dumpfile test_ra_sdr_32x32.vcd opened for output.
VCD warning: $dumpvars: Package ($unit) is not dumpable with VCD.
make[1]: Leaving directory '/media/wtf/WD_USBC_4T/projects/toy-sram/rtl/sim/coco'
vcd2fst test_ra_sdr_32x32.vcd test_ra_sdr_32x32.fst
#rm test_ra_sdr_32x32.vcd

```

```
gtkwave test_ra_sdr_32x32.fst wtf_test_ra_sdr_32x32.gtkw
```

## Test Site

* compile and run
50067.50ns INFO cocotb.tb_ra_64x72_2r1w [00050069] * RD COMPARE * port=1 adr=1A act=BD0918D335EAE57EB8 exp=BD0918D335EAE57EB8
50067.50ns INFO cocotb.tb_ra_64x72_2r1w [00050069] Port=0 RD @2D
50067.50ns INFO cocotb.tb_ra_64x72_2r1w [00050069] Port=1 RD @3C
50068.50ns INFO cocotb.tb_ra_64x72_2r1w [00050070] Port=0 RD @03
50069.50ns INFO cocotb.tb_ra_64x72_2r1w [00050071] * RD COMPARE * port=0 adr=2D act=DD22A03EC8ECED56A5 exp=DD22A03EC8ECED56A5
50069.50ns INFO cocotb.tb_ra_64x72_2r1w [00050071] * RD COMPARE * port=1 adr=3C act=E2D4702C0CFAF156D5 exp=E2D4702C0CFAF156D5
50069.50ns INFO cocotb.tb_ra_64x72_2r1w [00050071] Port=0 WR @27=2912D1F5B60C23A494
50069.50ns INFO cocotb.tb_ra_64x72_2r1w [00050071] Port=0 RD @2B
50070.50ns INFO cocotb.tb_ra_64x72_2r1w [00050072] * RD COMPARE * port=0 adr=03 act=37E14D57DAA64D10D7 exp=37E14D57DAA64D10D7
50070.50ns INFO cocotb.tb_ra_64x72_2r1w [00050072] Port=0 RD @01
50071.50ns INFO cocotb.tb_ra_64x72_2r1w [00050073] * RD COMPARE * port=0 adr=2B act=2637DB380BED8B3991 exp=2637DB380BED8B3991
50071.50ns INFO cocotb.tb_ra_64x72_2r1w [00050073] Port=0 WR @17=EC8135D0A0CE1AF036
50072.50ns INFO cocotb.tb_ra_64x72_2r1w [00050074] * RD COMPARE * port=0 adr=01 act=BAD2EFF3CF3A88BEF4 exp=BAD2EFF3CF3A88BEF4
50072.50ns INFO cocotb.tb_ra_64x72_2r1w [00050074] Port=0 WR @3E=DABCF1EB8186F007B4
50072.50ns INFO cocotb.tb_ra_64x72_2r1w [00050074] Port=0 RD @06
50073.50ns INFO cocotb.tb_ra_64x72_2r1w [00050075] Port=0 RD @2D
50074.50ns INFO cocotb.tb_ra_64x72_2r1w [00050076] * RD COMPARE * port=0 adr=06 act=119CDD1F186BC31FAC exp=119CDD1F186BC31FAC
50074.50ns INFO cocotb.tb_ra_64x72_2r1w [00050076] Port=0 WR @0E=F4852272F5E53D788B
50074.50ns INFO cocotb.tb_ra_64x72_2r1w [00050076] Port=1 RD @1F
50075.50ns INFO cocotb.tb_ra_64x72_2r1w [00050077] * RD COMPARE * port=0 adr=2D act=DD22A03EC8ECED56A5 exp=DD22A03EC8ECED56A5
50075.50ns INFO cocotb.tb_ra_64x72_2r1w [00050077] Port=0 RD @28
50076.50ns INFO cocotb.tb_ra_64x72_2r1w [00050078] * RD COMPARE * port=1 adr=1F act=DE5FE08C9855989C00 exp=DE5FE08C9855989C00
50076.50ns INFO cocotb.tb_ra_64x72_2r1w [00050078] Port=0 WR @13=F5B2F5D804B13021B0
50077.50ns INFO cocotb.tb_ra_64x72_2r1w [00050079] * RD COMPARE * port=0 adr=28 act=B867B78554C2B54D81 exp=B867B78554C2B54D81
50077.50ns INFO cocotb.tb_ra_64x72_2r1w [00050079] Port=0 WR @2A=83BA688D6465DCDB94
50079.50ns INFO cocotb.tb_ra_64x72_2r1w [00050081] Quiescing...
50089.00ns INFO cocotb.tb_ra_64x72_2r1w [00050091] Done.
50089.00ns INFO cocotb.tb_ra_64x72_2r1w [00050091] Final State

Reads Port 0: 19885
Reads Port 1: 19982
Writes Port 0: 19944
50089.00ns INFO cocotb.tb_ra_64x72_2r1w [00050091] You has opulence.
50089.00ns INFO cocotb.regression tb passed
50089.00ns INFO cocotb.regression **************************************************************************************
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
**************************************************************************************
** tb_ra_64x72.tb PASS 50089.00 57.99 863.71 **
**************************************************************************************
** TESTS=1 PASS=1 FAIL=0 SKIP=0 50089.00 58.21 860.44 **
**************************************************************************************

```
make -f Makefile_site build

```

* just run (tb.py changes, etc.)

```
make -f Makefile_site run

```

* results

```
0.00ns INFO Running on Icarus Verilog version 12.0 (devel)
0.00ns INFO Running tests with cocotb v1.7.0.dev0 from /home/wtf/.local/lib/python3.8/site-packages/cocotb
0.00ns INFO Seeding Python random module with 1655136638
0.00ns INFO Found test tb.tb_site
0.00ns INFO running tb_site (1/0)
ToySRAM site test
VCD info: dumpfile test_site.vcd opened for output.
VCD warning: $dumpvars: Package ($unit) is not dumpable with VCD.
0.00ns INFO [00000001] Resetting...
9.00ns INFO [00000010] Releasing reset.
15.00ns INFO [00000017] Writing Port 0 @00100000 00=633212F3
17.00ns INFO [00000019] Reading Port 0 @00100000 00
22.00ns INFO [00000024] Read Data: 633212F3
22.00ns INFO [00000024] Writing Port 0 @00100001 01=6A0278C9
24.00ns INFO [00000026] Reading Port 0 @00100001 01
29.00ns INFO [00000031] Read Data: 6A0278C9
...
1769.00ns INFO [00001770] Writing W0@15=08675309...
1769.00ns INFO [00001770] Scanning in...
1798.00ns INFO [00001800] ...tick...
1898.00ns INFO [00001900] ...tick...
1998.00ns INFO [00002000] ...tick...
2075.00ns INFO [00002076] Blipping RA0 clk...
2098.00ns INFO [00002100] ...tick...
2175.00ns INFO [00002176] Reading R0@15, R1@16...
2175.00ns INFO [00002176] Scanning in...
2198.00ns INFO [00002200] ...tick...
2298.00ns INFO [00002300] ...tick...
2398.00ns INFO [00002400] ...tick...
2481.00ns INFO [00002482] Blipping RA0 clk...
2498.00ns INFO [00002500] ...tick...
2581.00ns INFO [00002582] Blipping RA0 clk...
2598.00ns INFO [00002600] ...tick...
2681.00ns INFO [00002682] Blipping RA0 clk...
2698.00ns INFO [00002700] ...tick...
2781.00ns INFO [00002782] Scanning out...
2798.00ns INFO [00002800] ...tick...
2898.00ns INFO [00002900] ...tick...
2998.00ns INFO [00003000] ...tick...
3035.00ns INFO [00003036] ScanData=78433A984C075227A100000000000000
3035.00ns INFO [00003036] r0 adr:0F
3035.00ns INFO [00003036] r0 dat:08675309
3035.00ns INFO [00003036] r1 adr:10
3035.00ns INFO [00003036] r1 dat:1D489E84
3035.00ns INFO [00003036] w0 adr:00
3035.00ns INFO [00003036] w0 dat:00000000
3035.00ns INFO [00003036] cfg:00000
3035.00ns INFO [00003036] Done
3044.00ns INFO tb_site passed
3044.00ns INFO **************************************************************************************
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
**************************************************************************************
** tb.tb_site PASS 3044.00 0.87 3517.25 **
**************************************************************************************
** TESTS=0 PASS=1 FAIL=0 SKIP=0 3044.00 0.89 3420.87 **
**************************************************************************************
```

@ -0,0 +1,6 @@
<testsuites name="results">
<testsuite name="all" package="all">
<property name="random_seed" value="8675309" />
<testcase name="tb" classname="tb_ra_64x72" file="/data/projects/toy-sram/rtl/sim/coco/tb_ra_64x72.py" lineno="291" time="43.35837435722351" sim_time_ns="50089.001" ratio_time="1155.232449153278" />
</testsuite>
</testsuites>

Binary file not shown.

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

@ -1 +1 @@
../../src/array
../../src

Binary file not shown.

@ -1,5 +1,4 @@
# toysram sdr tb
# converted from pyverilator version
#
# variations:
# sdr: 1x
@ -372,10 +371,14 @@ async def tb(dut):
quiesced = False
quiesceCyc = sim.cycle + sim.maxCycles - 10
errors = 0
#rangesRd = [(0,63), (0,63), (0,63), (0,63)]
rangesRd = [(0,7), (0,7), (0,7), (0,7)]
#rangesWr = [(0,63), (0,63),(0,63), (0,63)]
rangesWr = [(0,7), (0,7)]

# configure allowed ports/entries
rangesRd = [(0,63), (0,63), (0,63), (0,63)] # full
#rangesRd = [(0,7), (0,7), (0,7), (0,7)] # hammer
rangesWr = [(0,63), (0,63),(0,63), (0,63)] # full
#rangesWr = [(0,7), (0,7)] # hammer
#rangesWr = [None, None] # none

verbose = True

for c in range(sim.maxCycles):
@ -430,7 +433,7 @@ async def tb(dut):
for i in range(len(portsWr)):
portsWr[i].idle()
aw[i] = -1
if not quiesced and randint(1, 10) < 5:
if rangesWr[i] is not None and not quiesced and randint(1, 10) < 5:
r = rangesWr[i]
aw[i] = randint(r[0], r[1])
d = int(hexrandom(18), 16)
@ -440,7 +443,7 @@ async def tb(dut):

for i in range(len(portsRd)):
portsRd[i].idle()
if not quiesced and randint(1, 10) < 5:
if rangesRd[i] is not None and not quiesced and randint(1, 10) < 5:
r = rangesRd[i]
ar = randint(r[0], r[1])
while ar == aw[0] or ar == aw[1]:

File diff suppressed because it is too large Load Diff

@ -0,0 +1,129 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Array wrapper for cocotb/icarus
// 64 word 72 bit logical array, 2R1W (SDR)
// LCB for strobe generation
// Config, BIST, etc.

`timescale 1 ns / 1 ns

module tb_ra_64x72_2r1w (

input clk,
input reset,
input cfg_wr,
input [0:31] cfg_dat,
input [0:31] bist_ctl,
output [0:31] bist_status,

input rd_enb_0,
input [0:5] rd_adr_0,
output [0:71] rd_dat_0,

input rd_enb_1,
input [0:5] rd_adr_1,
output [0:71] rd_dat_1,

input wr_enb_0,
input [0:5] wr_adr_0,
input [0:71] wr_dat_0

);

wire strobe;
wire [0:31] cfg;
wire mux_rd0_enb;
wire [0:5] mux_rd0_adr;
wire mux_rd1_enb;
wire [0:5] mux_rd1_adr;
wire mux_wr0_enb;
wire [0:5] mux_wr0_adr;
wire [0:71] mux_wr0_dat;

initial begin
$dumpfile ("tb_ra_64x72.vcd");
$dumpvars;
#1;
end

ra_lcb_sdr lcb (

.clk (clk),
.reset (reset),
.cfg (cfg),
.strobe (strobe)

);

ra_cfg_sdr #(.INIT(-1)) cnfig (

.clk (clk),
.reset (reset),
.cfg_wr (cfg_wr),
.cfg_dat (cfg_dat),
.cfg (cfg)

);

ra_bist_sdr bist (

.clk (clk),
.reset (reset),
.ctl (bist_ctl),
.status (bist_status),
.rd0_enb_in (rd_enb_0),
.rd0_adr_in (rd_adr_0),
.rd0_dat (rd_dat_0),
.rd1_enb_in (rd_enb_1),
.rd1_adr_in (rd_adr_1),
.rd1_dat (rd_dat_1),
.wr0_enb_in (wr_enb_0),
.wr0_adr_in (wr_adr_0),
.wr0_dat_in (wr_dat_0),
.rd0_enb_out (mux_rd0_enb),
.rd0_adr_out (mux_rd0_adr),
.rd1_enb_out (mux_rd1_enb),
.rd1_adr_out (mux_rd1_adr),
.wr0_enb_out (mux_wr0_enb),
.wr0_adr_out (mux_wr0_adr),
.wr0_dat_out (mux_wr0_dat)

);

ra_64x72_2r1w ra (

.clk (clk),
.reset (reset),
.strobe (strobe),
.rd_enb_0 (mux_rd0_enb),
.rd_adr_0 (mux_rd0_adr),
.rd_dat_0 (rd_dat_0),
.rd_enb_1 (mux_rd1_enb),
.rd_adr_1 (mux_rd1_adr),
.rd_dat_1 (rd_dat_1),
.wr_enb_0 (mux_wr0_enb),
.wr_adr_0 (mux_wr0_adr),
.wr_dat_0 (mux_wr0_dat)

);

endmodule

@ -1,148 +0,0 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Test array (SDR) wrapper for cocotb/icarus
// 32 word 32 bit array
// LCB for strobe generation
// Config, BIST, etc.

`timescale 1 ns / 1 ns

`include "toysram.vh"

module test_ra_sdr_32x32 (

clk,
reset,
cfg_wr,
cfg_dat,
bist_ctl,
bist_status,

rd_enb_0,
rd_adr_0,
rd_dat_0,

rd_enb_1,
rd_adr_1,
rd_dat_1,

wr_enb_0,
wr_adr_0,
wr_dat_0

);

input clk;
input reset;
input cfg_wr;
input [0:`LCBSDR_CONFIGWIDTH-1] cfg_dat;
input [0:31] bist_ctl;
output [0:31] bist_status;
input rd_enb_0;
input [0:4] rd_adr_0;
output [0:31] rd_dat_0;
input rd_enb_1;
input [0:4] rd_adr_1;
output [0:31] rd_dat_1;
input wr_enb_0;
input [0:4] wr_adr_0;
input [0:31] wr_dat_0;

wire strobe;
wire [0:`LCBSDR_CONFIGWIDTH-1] cfg;
wire mux_rd0_enb;
wire [0:4] mux_rd0_adr;
wire mux_rd1_enb;
wire [0:4] mux_rd1_adr;
wire mux_wr0_enb;
wire [0:4] mux_wr0_adr;
wire [0:31] mux_wr0_dat;


initial begin
$dumpfile ("test_ra_sdr_32x32.vcd");
$dumpvars;
#1;
end

ra_lcb_sdr lcb (

.clk (clk),
.reset (reset),
.cfg (cfg),
.strobe (strobe)

);

ra_cfg_sdr #(.INIT(-1)) cfig (

.clk (clk),
.reset (reset),
.cfg_wr (cfg_wr),
.cfg_dat (cfg_dat),
.cfg (cfg)

);

ra_bist_sdr_32x32 bist (

.clk (clk),
.reset (reset),
.ctl (bist_ctl),
.status (bist_status),
.rd0_enb_in (rd_enb_0),
.rd0_adr_in (rd_adr_0),
.rd0_dat (rd_dat_0),
.rd1_enb_in (rd_enb_1),
.rd1_adr_in (rd_adr_1),
.rd1_dat (rd_dat_1),
.wr0_enb_in (wr_enb_0),
.wr0_adr_in (wr_adr_0),
.wr0_dat_in (wr_dat_0),
.rd0_enb_out (mux_rd0_enb),
.rd0_adr_out (mux_rd0_adr),
.rd1_enb_out (mux_rd1_enb),
.rd1_adr_out (mux_rd1_adr),
.wr0_enb_out (mux_wr0_enb),
.wr0_adr_out (mux_wr0_adr),
.wr0_dat_out (mux_wr0_dat)

);

ra_2r1w_32x32_sdr ra (

.clk (clk),
.reset (reset),
.strobe (strobe),
.rd_enb_0 (mux_rd0_enb),
.rd_adr_0 (mux_rd0_adr),
.rd_dat_0 (rd_dat_0),
.rd_enb_1 (mux_rd1_enb),
.rd_adr_1 (mux_rd1_adr),
.rd_dat_1 (rd_dat_1),
.wr_enb_0 (mux_wr0_enb),
.wr_adr_0 (mux_wr0_adr),
.wr_dat_0 (mux_wr0_dat)

);

endmodule

File diff suppressed because it is too large Load Diff

Binary file not shown.

@ -1,65 +0,0 @@
[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Wed Jun 8 15:39:53 2022
[*]
[dumpfile] "/media/wtf/WD_USBC_4T/projects/toy-sram/rtl/sim/coco/test_ra_sdr_32x32.fst"
[dumpfile_mtime] "Wed Jun 8 15:03:44 2022"
[dumpfile_size] 4425
[savefile] "/media/wtf/WD_USBC_4T/projects/toy-sram/rtl/sim/coco/wtf_test_ra_sdr_32x32.gtkw"
[timestart] 19240
[size] 2088 1240
[pos] 218 58
*-12.000000 30000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] test_ra_sdr_32x32.
[treeopen] test_ra_sdr_32x32.ra.
[treeopen] test_ra_sdr_32x32.ra.array0.
[sst_width] 282
[signals_width] 312
[sst_expanded] 1
[sst_vpaned_height] 370
@28
test_ra_sdr_32x32.clk
@200
-WR 0
@28
test_ra_sdr_32x32.wr_enb_0
@22
test_ra_sdr_32x32.wr_adr_0[0:4]
test_ra_sdr_32x32.wr_dat_0[0:31]
@200
-RD 0
@28
test_ra_sdr_32x32.rd_enb_0
@22
test_ra_sdr_32x32.rd_adr_0[0:4]
test_ra_sdr_32x32.rd_dat_0[0:31]
@200
-RD 1
@28
test_ra_sdr_32x32.rd_enb_1
@22
test_ra_sdr_32x32.rd_adr_1[0:4]
test_ra_sdr_32x32.rd_dat_1[0:31]
@200
-RA
-RA[0]
@22
test_ra_sdr_32x32.ra.array0.ra[0].q[0:31]
test_ra_sdr_32x32.ra.array0.ra[1].q[0:31]
test_ra_sdr_32x32.ra.array0.ra[2].q[0:31]
test_ra_sdr_32x32.ra.array0.ra[3].q[0:31]
test_ra_sdr_32x32.ra.array0.ra[4].q[0:31]
test_ra_sdr_32x32.ra.array0.ra[5].q[0:31]
test_ra_sdr_32x32.ra.array0.ra[6].q[0:31]
@23
test_ra_sdr_32x32.ra.array0.ra[7].q[0:31]
@28
test_ra_sdr_32x32.ra.array0.wr0_a0
test_ra_sdr_32x32.ra.array0.wr0_a1
test_ra_sdr_32x32.ra.array0.wr0_a1_a2
test_ra_sdr_32x32.ra.array0.wr0_a1_na2
test_ra_sdr_32x32.ra.array0.wr0_a2
test_ra_sdr_32x32.ra.array0.wr0_a3
test_ra_sdr_32x32.ra.array0.wr0_a4
[pattern_trace] 1
[pattern_trace] 0

@ -1,68 +0,0 @@
[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Thu May 26 19:05:29 2022
[*]
[dumpfile] "/home/wtf/projects/toysram-opf/rtl/sim/coco/test_ra_sdr_64x72.fst"
[dumpfile_mtime] "Thu May 26 18:50:01 2022"
[dumpfile_size] 12003
[savefile] "/home/wtf/projects/toysram-opf/rtl/sim/coco/wtf_test_ra_sdr_64x72.gtkw"
[timestart] 89538
[size] 2088 1240
[pos] 218 58
*-10.000000 94187 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] test_ra_sdr_64x72.
[treeopen] test_ra_sdr_64x72.ra.
[treeopen] test_ra_sdr_64x72.ra.array2.
[sst_width] 282
[signals_width] 312
[sst_expanded] 1
[sst_vpaned_height] 370
@28
test_ra_sdr_64x72.clk
test_ra_sdr_64x72.reset
@200
-WR 0
@29
test_ra_sdr_64x72.wr_enb_0
@22
test_ra_sdr_64x72.wr_adr_0[0:5]
test_ra_sdr_64x72.wr_dat_0[0:71]
@200
-RD 0
@28
test_ra_sdr_64x72.rd_enb_0
@22
test_ra_sdr_64x72.rd_adr_0[0:5]
test_ra_sdr_64x72.rd_dat_0[0:71]
@200
-RD 1
@28
test_ra_sdr_64x72.rd_enb_1
@22
test_ra_sdr_64x72.rd_adr_1[0:5]
test_ra_sdr_64x72.rd_dat_1[0:71]
@200
-RA
@28
test_ra_sdr_64x72.ra.rd_enb_0_q
@22
test_ra_sdr_64x72.ra.rd_adr_0_q[0:5]
test_ra_sdr_64x72.ra.rd_dat_0_q[0:71]
@28
test_ra_sdr_64x72.ra.rd_enb_1_q
@22
test_ra_sdr_64x72.ra.rd_adr_1_q[0:5]
test_ra_sdr_64x72.ra.rd_dat_1_q[0:71]
@28
test_ra_sdr_64x72.ra.wr_enb_0_q
@22
test_ra_sdr_64x72.ra.wr_adr_0_q[0:5]
test_ra_sdr_64x72.ra.wr_dat_0_q[0:71]
@200
-RA[0]
@22
test_ra_sdr_64x72.ra.array0.ra[0].q[0:23]
test_ra_sdr_64x72.ra.array1.ra[0].q[0:23]
test_ra_sdr_64x72.ra.array2.ra[0].q[0:23]
[pattern_trace] 1
[pattern_trace] 0

@ -1,138 +0,0 @@
[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Mon Jun 13 17:02:24 2022
[*]
[dumpfile] "/media/wtf/WD_USBC_4T/projects/toy-sram/rtl/sim/coco/test_site.fst"
[dumpfile_mtime] "Mon Jun 13 16:51:29 2022"
[dumpfile_size] 408816
[savefile] "/media/wtf/WD_USBC_4T/projects/toy-sram/rtl/sim/coco/wtf_test_site.gtkw"
[timestart] 2034000
[size] 2048 1078
[pos] 206 125
*-18.000000 3035000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] test_site.
[treeopen] test_site.site.
[treeopen] test_site.site.ra_0.
[treeopen] test_site.site.ra_0.ra.
[sst_width] 204
[signals_width] 265
[sst_expanded] 1
[sst_vpaned_height] 314
@28
test_site.wb_clk_i
test_site.wb_rst_i
test_site.wbs_cyc_i
test_site.wbs_stb_i
test_site.wbs_we_i
@22
test_site.wbs_adr_i[31:0]
test_site.wbs_sel_i[3:0]
test_site.wbs_dat_i[31:0]
@28
test_site.wbs_ack_o
@22
test_site.wbs_dat_o[31:0]
test_site.la_data_in[127:0]
test_site.la_data_out[127:0]
test_site.la_oenb[127:0]
test_site.io_in[37:0]
test_site.io_oeb[37:0]
test_site.io_out[37:0]
@28
test_site.irq[2:0]
@200
-WB SLAVE
@22
test_site.site.wb.rd_dat[31:0]
@28
test_site.site.wb.rd_ack_q
@22
test_site.site.wb.rd_dat_q[31:0]
@200
-CFG
@22
test_site.site.cfg.cfg0_q[31:0]
@28
test_site.site.cfg.wb_cmd_val
test_site.site.cfg.cfg_cmd_val
test_site.site.cfg.ctl_cmd_val
test_site.site.cfg.ra0_cmd_val
@22
test_site.site.cfg.cmd_adr[31:0]
@28
test_site.site.cfg.cmd_we
@22
test_site.site.cfg.cmd_sel[3:0]
test_site.site.cfg.cmd_dat[31:0]
@200
-CTL
@22
test_site.site.ctl.io_in[37:0]
test_site.site.ctl.io_out[37:0]
test_site.site.ctl.io_oeb[37:0]
test_site.site.cfg.cfg0_q[31:0]
test_site.site.ctl.seq_q[4:0]
@28
test_site.site.ctl.ctl_cmd_val
test_site.site.ctl.ra0_cmd_val
test_site.site.ctl.adr_bist
test_site.site.ctl.adr_config
@22
test_site.site.ctl.cmd_adr[31:0]
@28
test_site.site.ctl.cmd_we
@22
test_site.site.ctl.cmd_sel[3:0]
test_site.site.ctl.cmd_dat[31:0]
@28
test_site.site.ctl.rd_ack
test_site.site.ctl.rdata_sel[2:0]
@22
test_site.site.ctl.rd_dat[31:0]
@28
test_site.site.ctl.ra0_r0_enb
@22
test_site.site.ctl.ra0_r0_adr[4:0]
test_site.site.ctl.ra0_r0_dat[31:0]
@28
test_site.site.ctl.ra0_r1_enb
@22
test_site.site.ctl.ra0_r1_adr[4:0]
test_site.site.ctl.ra0_r1_dat[31:0]
@28
test_site.site.ctl.ra0_w0_enb
@22
test_site.site.ctl.ra0_w0_adr[4:0]
test_site.site.ctl.ra0_w0_dat[31:0]
@28
test_site.site.ctl.test_enable
@22
test_site.site.ctl.scan_reg_q[127:0]
@28
test_site.site.ctl.scan_clk
@22
test_site.site.ctl.scan_config[16:0]
@28
test_site.site.ctl.scan_di
test_site.site.ctl.scan_do
test_site.site.ctl.io_ra0_clk
test_site.site.ctl.io_ra0_rst
@200
-RA0
@28
test_site.site.ra_0.clk
test_site.site.ra_0.ra.wr_enb_0_q
@22
test_site.site.ra_0.ra.wr_adr_0_q[0:4]
test_site.site.ra_0.ra.wr_dat_0_q[0:31]
@28
test_site.site.ra_0.ra.rd_enb_0_q
@22
test_site.site.ra_0.ra.rd_dat_0_q[0:31]
@28
test_site.site.ra_0.ra.rd_enb_1_q
@22
test_site.site.ra_0.ra.rd_dat_1_q[0:31]
test_site.site.ra_0.ra.array0.ra[0].q[0:31]
[pattern_trace] 1
[pattern_trace] 0

File diff suppressed because it is too large Load Diff

@ -1,113 +0,0 @@
# Utilities

import random

# printing

me = ' pys--. '
quiet = False
getSimTime = None

def msg(text='', lvl=0, name=None, init=None):
global me, quiet, getSimTime

if init is not None:
getSimTime = init
return

if quiet and lvl != 0:
return

if name is None:
name = me
if getSimTime is not None:
t,c = getSimTime()
else:
t,c = (0,0)
s = f'{t:08d}[{c:08d}] {name:>8}: '
pad = ' ' * len(s)

text = text + '\n'
lines = text.splitlines()
s = s + lines[0] + '\n'
for i in range(1, len(lines)):
s = s + pad
s = s + lines[i] + '\n'
print(s[0:-1])

# randoms

def intrandom(n):
return random.randint(0, n-1)

def hexrandom(w=16):
n = random.getrandbits(w*4)
return '{0:0{l}X}'.format(n, l=w)

def binrandom(w=32):
n = random.getrandbits(w)
return '{0:0>{l}b}'.format(n, l=w)

def randOK(freq):
v = random.randint(1,100) # 1 <= v <= 100
if freq == 0:
return False
else:
return v <= freq

# weights is either
# a simple list: return weighted index
# a list of tuple(val, weight): return weighted val
def randweighted(weights):

if len(weights) == 0:
return 0

if type(weights[0]) is tuple:
vals = []
tWeights = []
for i in range (0, len(weights)):
vals.append(weights[i][0])
tWeights.append(weights[i][1])
weights = tWeights
else:
vals = range(0, len(weights))

sum = 0
for i in range(0, len(weights)):
sum = sum + weights[i]
v = random.randint(0,sum-1)
weight = 0
for i in range(0, len(weights)):
weight = weight + weights[i]
if v < weight:
break

return vals[i]

# converters

def b2x(b, w=None):
if w is None:
rem = len(b) % 4
w = len(b)/4
if rem != 0:
w = w + 1
return '{0:0{l}X}'.format(int(b,2), l=w)

def x2b(x, w=None):
i = int(str(x),16)
if w is None:
return bin(i)[2:]
else:
return '{0:0>{l}s}'.format(bin(i)[2:], l=w)

def d2x(x, w=None):
#return hex(int(x)).split('x')[-1].upper()
if w is None:
return '{0:X}'.format(x)
else:
return '{0:0{l}X}'.format(x, l=w)

def x2d(i):
return int(i, 16)

@ -1 +0,0 @@
/home/wtf/projects/pyverilator_no_uart/pyverilator

@ -1,444 +0,0 @@
#!/usr/bin/python3

# pyverilator
# fixed internal sig parsing (cdata/wdata)
# 1. this should be based on init setting AND should be done even w/o trace on!!!
# in add_to_vcd_trace(self), time is bumped +5
# 2. should count cycs
# 3. add parm so clock can be set but NOT eval (for multiclock, only fastest evals)
# 4. how to access mem[][]??
# 5. not adding vectors to gtk - cuz 0:n?

import os, sys
import datetime
from optparse import OptionParser
from optparse import OptionGroup

import random
from random import randint

from pysutils import *

user = os.environ['USER']
binPath = os.path.dirname(os.path.realpath(__file__))

localPV = True
if localPV:
import os, sys
sys.path.append(os.path.join(binPath, 'pyverilator'))
import pyverilator

####################################################################
# Defaults

rtl = ['src']
model = 'sdr'

stopOnFail = True
verbose = False
vcd = False
seed = randint(1, int('8675309', 16))
runCycs = 100

#rangesRd = [(0,63), (0,63), (0,63), (0,63)]
rangesRd = [(0,7), (0,7), (0,7), (0,7)]
#rangesWr = [(0,63), (0,63)]
rangesWr = [(0,7), (0,7)]


####################################################################
# Process command line

usage = "Usage: %prog [options]"
parser = OptionParser(usage)

parser.add_option('-m', '--model', dest='model', help=f'sdr or ddr')
parser.add_option('-s', '--seed', dest='seed', help=f'initialize seed to n')
parser.add_option('-c', '--cycles', dest='runCycs', help=f'cycles to run, default={runCycs}')

parser.add_option('-t', '--trace', dest='trace', action='store_true', help=f'create wave file')
parser.add_option('-f', '--stopfail', dest='stopOnFail', action='store_true', help=f'stop on first fail')

parser.add_option('-v', '--verbose', dest='verbose', action='store_true', help=f'noisy output')

options, args = parser.parse_args()

if options.model is not None:
model = options.model

if options.seed is not None:
seed = int(options.seed)

if options.runCycs is not None:
runCycs = int(options.runCycs)

if options.trace is not None:
vcd = True

if options.stopOnFail is not None:
stopOnFail = True

if options.verbose is not None:
verbose = True

####################################################################
# Init

sdr = False
ddr = False
ddr1x = False

if model == 'sdr':
top = 'test_ra_sdr.v'
sdr = True
elif model == 'ddr1x':
top = 'test_ra_ddr_1x.v'
ddr = True
ddr1x = True
else:
top = 'test_ra_ddr.v'
ddr = True

errors = 0
cyc = 0
quiesceCyc = 5 # before end

# build model
sim = pyverilator.PyVerilator.build(top, verilog_path=rtl)
print('io')
print(sim.io)
print()

print('internals')
# issue #8 - try local fix
print(sim.internals)
print()

#print('ra')
#print(sim.internals.ra)
# array0,1,2 dont exist as submodules???
#print()
#
#print('ra.add_clk')
#print(sim.internals.ra.add_clk)
#print()

if vcd:
sim.start_gtkwave(auto_tracing=False)

#wtf vectors are failing
# will make this load a savefile anyway someday
# this doesn't actually restrict what's beign recorded anyway; still
# can load saved netlist after sim
#sim.send_to_gtkwave(sim.io)
#for s in sim.io:
# try:
# sim.send_to_gtkwave(sim.io[s])
# except:
# print(f'*** failed {s}')

####################################################################
# Functions, Classes

def getSimTime():
return (sim.curr_time, cyc)
msg(init=getSimTime)

# sim-driven signals don't look like _q since they are set after the eval(clk=1) tick
# would have to set after eval of rising edge but also not do a simtick
def tick():
sim.eval()
if vcd:
sim.add_to_vcd_trace()

def run(n=1, cb=None):
global cyc

if sdr or ddr1x:
for i in range(n):
sim.io.clk = 0
tick()
sim.io.clk = 1
tick()
elif ddr:
for i in range(n):
sim.io.clk = 0
sim.io.clk2x = 1
tick()
sim.io.clk2x = 0
tick()
sim.io.clk = 1
sim.io.clk2x = 1
tick()
sim.io.clk2x = 0
tick()

cyc += 1
if not vcd: # should be done by pyv!!!!
sim.curr_time = cyc * 10
if cb is not None:
(cb)()

def fail(t=None):
global errors, stopOnFail
msg('*** FAIL ***')
errors += 1
if t is not None:
msg(t)

class Memory:

def __init__(self, locs, bits, init=0):
self.mem = [init] * locs
self.bits = bits

def read(self, adr):
return self.mem[adr]

def readall(self):
mem = []
for i in range(len(self.mem)):
mem.append(self.mem[i])
return mem

def write(self, adr, dat):
self.mem[adr] = dat

def __str__(self):
t = ''
for i in range(0,len(self.mem),4):
t1 = f'[{i:02X}] {self.mem[i]:018X}'
for j in range(i+1, i+4):
t1 += f' [{j:02X}] {self.mem[j]:018X}'
#t1 += f' {self.mem[j]:018X}\n'
t += t1 + '\n'
return t

class Port:

def __init__(self, id, type='r'):
self.id = id
self.type = type

def read(self, adr):
sim.io[f'rd_enb_{self.id}'] = 1
sim.io[f'rd_adr_{self.id}'] = adr
msg(f'Port={self.id} RD @{adr:02X}')
def write(self, adr, dat):
sim.io[f'wr_enb_{self.id}'] = 1
sim.io[f'wr_adr_{self.id}'] = adr
sim.io[f'wr_dat_{self.id}'] = dat
msg(f'Port={self.id} WR @{adr:02X}={dat:02X}')

def data(self):
return int(sim.io[f'rd_dat_{self.id}'])

def idle(self):
if self.type == 'r':
sim.io[f'rd_enb_{self.id}'] = 0
sim.io[f'rd_adr_{self.id}'] = 0 # random
else:
sim.io[f'wr_enb_{self.id}'] = 0
sim.io[f'wr_adr_{self.id}'] = 0 # random
sim.io[f'wr_dat_{self.id}'] = 0 # random

def printstate():
mac = sim.internals.ra
if sdr:
msg(f'R0: {mac.rd_enb_0_q:01X} {mac.rd_adr_0_q:02X} {mac.rd_dat_0_q:018X} R1: {mac.rd_enb_1_q:01X} {mac.rd_adr_1_q:02X} {mac.rd_dat_1_q:018X}')
msg(f'W0: {mac.wr_enb_0_q:01X} {mac.wr_adr_0_q:02X} {mac.wr_dat_0_q:018X}')
else:
msg(f'R0: {mac.rd_enb_0_q:01X} {mac.rd_adr_0_q:02X} {mac.rd_dat_0_q:018X} R1: {mac.rd_enb_1_q:01X} {mac.rd_adr_1_q:02X} {mac.rd_dat_1_q:018X} R2: {mac.rd_enb_2_q:01X} {mac.rd_adr_2_q:02X} {mac.rd_dat_2_q:018X} R3: {mac.rd_enb_3_q:01X} {mac.rd_adr_3_q:02X} {mac.rd_dat_3_q:018X}')
msg(f'W0: {mac.wr_enb_0_q:01X} {mac.wr_adr_0_q:02X} {mac.wr_dat_0_q:018X} W1: {mac.wr_enb_1_q:01X} {mac.wr_adr_1_q:02X} {mac.wr_dat_1_q:018X}')

def printfinal():

print()
print()
print('Final State')
print(f'Model : {top}')
print()
print(data)
# should be checking actual mem[][] here, but can't access signals
print()
for i in range(len(portsRd)):
print(f'Reads Port {i}: {reads[i]}')
for i in range(len(portsWr)):
print(f'Writes Port {i}: {writes[i]}')
print()
print(f'Seed: {seed:08X}')
print(f'Cycles: {cyc}')
print(f'Errors: {errors}')

def check(port, adr, exp=None):

if exp is None:
exp = data.read(adr)
act = portsRd[port].data()
if act != exp:
fail(f'* RD MISCOMPARE * port={port} adr={adr:02X} act={act:018X} exp={exp:018X}')
return False
elif verbose:
msg(f'* RD COMPARE * port={port} adr={adr:02X} act={act:018X} exp={exp:018X}')
return True

####################################################################
# Do something

msg(f'Initializing seed to {hex(seed)}')

random.seed(seed)

data = Memory(64, 72)
if sdr:
portsRd = [Port(0, 'r'), Port(1, 'r')]
portsWr = [Port(0, 'w')]
else:
portsRd = [Port(0, 'r'), Port(1, 'r'), Port(2, 'r'), Port(3, 'r')]
portsWr = [Port(0, 'w'), Port(1, 'w')]

# Array Cycle Timings
#
# write
# | e/a/d | acc | valid |
# * latched by wrapper (in)
#
#
# read
# | e/a | acc | valid |
# * latched by wrapper (in)
# * latched by wrapper (out)
#
# rd(a) = wr(a) (both enabled):


# reset
sim.io.reset = 1
run(1)
sim.io.reset = 0

# idle
for p in portsRd:
p.idle()
for p in portsWr:
p.idle()

run(10)

# init array
if sdr:
for a in range(0, 64, 1):
d0 = int(f'5555555555555555{a:02X}', 16)
portsWr[0].write(a, d0)
run(1, printstate)
data.write(a, d0) # now visible for reads
portsWr[0].idle()
else:
for a in range(0, 64, 2):
d0 = int(f'5555555555555555{a:02X}', 16)
portsWr[0].write(a, d0)
d1 = int(f'5555555555555555{a+1:02X}', 16)
portsWr[1].write(a+1, d1)
run(1, printstate)
data.write(a, d0) # now visible for reads
data.write(a+1, d1) # now visible for reads
portsWr[0].idle()
portsWr[1].idle()

# random cmds
# writes: visible to all reads in cycle n+1,...
# reads: check in cycle n+2 vs mem data in cycle n+1
#
# every cycle:
# save data state
# pick weighted read0, read1, read2, read3, write0, write1 (cmd freq, adr) and ensure no adr coll if req'd
# schedule data change (write)
# schedule checks (read)

updates = []
checks = []
reads = [0, 0, 0, 0]
writes = [0, 0]
saveData = None
quiesced = False
quiesceCyc = cyc + runCycs - quiesceCyc

#d = int('1000', 16)
msg('Starting random loop.')
for c in range(runCycs):

ok = True

# check reads
checksNext = []
for i in range(len(checks)):
rd = checks[i]
if cyc == rd[0]:
ok = ok and check(rd[1], rd[2], saveData[rd[2]])
else:
checksNext.append(rd)
checks = checksNext

# do writes
updatesNext = [] # always only 1 cycle
for i in range(len(updates)):
wr = updates[i]
if cyc == wr[0]:
data.write(wr[2], wr[3])
else:
print('HUH? should always be this cycle!', cyc, updates)
quit()
updates = updatesNext

# save current data
saveData = data.readall()

# quiesce?
if cyc >= quiesceCyc:
if not quiesced:
msg('Quiescing...')
quiesced = True

# write coll will give w1 precedence - or make it avoid
aw = [None] * 2
for i in range(len(portsWr)):
portsWr[i].idle()
aw[i] = -1
if not quiesced and randint(1, 10) < 5:
r = rangesWr[i]
aw[i] = randint(r[0], r[1])
d = int(hexrandom(18), 16)
portsWr[i].write(aw[i], d)
updates.append((cyc+1, i, aw[i], d))
writes[i] += 1

for i in range(len(portsRd)):
portsRd[i].idle()
if not quiesced and randint(1, 10) < 5:
r = rangesRd[i]
ar = randint(r[0], r[1])
while ar == aw[0] or ar == aw[1]:
ar = randint(r[0], r[1])
portsRd[i].read(ar)
checks.append((cyc+2, i, ar))
reads[i] += 1

run(1, printstate)
if not ok and stopOnFail:
break

####################################################################
# Clean up

printfinal()

if ok and errors == 0:
print()
print('You has opulence.')
print()
else:
print()
print('You are worthless and weak!')
print()

print('Done.')

@ -1,22 +1,7 @@
# Functional verification of array and site logic

### CURRENT (cocotb+iverilog)
* cocotb, iverilog
* random reads/writes using 64x72 logical array and wrapper

* using cocotb instead of pyverilator [cocotb sim](./coco)


### OLD (pyverilator)

## check rtl

```
verilator --lint-only -Isrc -Wno-LITENDIAN src/test_ra_sdr.v
```

### build/sim

***not working at all with verilator v4.210***

```
sim -m sdr -c 1000 -t
```

File diff suppressed because it is too large Load Diff

@ -1,64 +0,0 @@
[*]
[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
[*] Tue Aug 17 12:25:53 2021
[*]
[dumpfile] "/home/wtf/projects/Skywater-Array-Site/opf-move/dev/sim/gtkwave.vcd"
[dumpfile_mtime] "Tue Aug 17 12:19:36 2021"
[dumpfile_size] 49576
[savefile] "/home/wtf/projects/Skywater-Array-Site/opf-move/dev/sim/wtf.gtkw"
[timestart] 1484
[size] 1416 1043
[pos] 30 53
*-5.931902 455 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP.
[treeopen] TOP.test_ra_ddr.
[treeopen] TOP.test_ra_ddr.ra.
[sst_width] 236
[signals_width] 185
[sst_expanded] 1
[sst_vpaned_height] 252
@28
TOP.test_ra_ddr.clk
TOP.test_ra_ddr.clk2x
TOP.test_ra_ddr.reset
TOP.test_ra_ddr.cfg_wr
TOP.test_ra_ddr.rd_enb_0
TOP.test_ra_ddr.rd_enb_1
TOP.test_ra_ddr.rd_enb_2
TOP.test_ra_ddr.rd_enb_3
TOP.test_ra_ddr.wr_enb_0
TOP.test_ra_ddr.wr_enb_1
@200
-RA FF
@28
TOP.test_ra_ddr.ra.rd_enb_0_q
@22
TOP.test_ra_ddr.ra.rd_adr_0_q[0:5]
TOP.test_ra_ddr.ra.rd_dat_0_q[0:71]
@28
TOP.test_ra_ddr.ra.rd_enb_1_q
@22
TOP.test_ra_ddr.ra.rd_adr_1_q[0:5]
TOP.test_ra_ddr.ra.rd_dat_1_q[0:71]
@28
TOP.test_ra_ddr.ra.rd_enb_2_q
@22
TOP.test_ra_ddr.ra.rd_adr_2_q[0:5]
TOP.test_ra_ddr.ra.rd_dat_2_q[0:71]
@28
TOP.test_ra_ddr.ra.rd_enb_3_q
@22
TOP.test_ra_ddr.ra.rd_adr_3_q[0:5]
TOP.test_ra_ddr.ra.rd_dat_3_q[0:71]
@28
TOP.test_ra_ddr.ra.wr_enb_0_q
@22
TOP.test_ra_ddr.ra.wr_adr_0_q[0:5]
TOP.test_ra_ddr.ra.wr_dat_0_q[0:71]
@28
TOP.test_ra_ddr.ra.wr_enb_1_q
@22
TOP.test_ra_ddr.ra.wr_adr_1_q[0:5]
TOP.test_ra_ddr.ra.wr_dat_1_q[0:71]
[pattern_trace] 1
[pattern_trace] 0

@ -1,110 +0,0 @@
[*]
[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
[*] Tue Aug 17 21:47:47 2021
[*]
[dumpfile] "/home/wtf/projects/Skywater-Array-Site/opf-move/dev/sim/gtkwave.vcd"
[dumpfile_mtime] "Tue Aug 17 21:22:27 2021"
[dumpfile_size] 57523
[savefile] "/home/wtf/projects/Skywater-Array-Site/opf-move/dev/sim/wtf_ddr.gtkw"
[timestart] 1663
[size] 1552 1029
[pos] 66 61
*-4.931902 1691 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1