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master
caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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microwatt/fpga
History
Paul Mackerras bf55efec6d Arty A7: Add an option to select the number of CPU cores 
Timing is currently not very good with 2 cores on the Arty A7-100.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 		3 weeks ago
..
LICENSE
…
acorn-cle-215.xdc acorn: Add support for the Acorn CLE 215+ 5 years ago
antmicro_artix_dc_scm.xdc antmicro-artix-dc-scm: Add Ethernet pins 2 years ago
arty_a7.xdc arty a7: Fix build error with Vivado (#429) 10 months ago
clk_gen_bypass.vhd
…
clk_gen_ecp5.vhd ECP5: Adjust PLL constants so the PLL lock indication works 3 years ago
clk_gen_mcmm.vhd Fix some whitespace issues 4 years ago
clk_gen_plle2.vhd fpga/clk_gen_plle2: Add support for 50Mhz->100Mhz 3 years ago
cmod_a7-35.xdc Remove -add from xdc files 4 years ago
firmware.hex
…
fpga-random.vhdl Add random number generator and implement the darn instruction 5 years ago
fpga-random.xdc Add random number generator and implement the darn instruction 5 years ago
genesys2.xdc Remove -waveform from xdc files 4 years ago
hello_world.hex
…
main_bram.vhdl Rename 'do' signal to avoid verilator System Verilog warning 4 years ago
nexys-video.xdc litesdcard: Add Nexys Video support 4 years ago
nexys_a7.xdc Remove -add from xdc files 4 years ago
pp_fifo.vhd
…
pp_soc_uart.vhd uart: Remove combinational loops on ack and stall signal 5 years ago
pp_utilities.vhd
…
soc_reset.vhdl soc_reset: Use counters, add synchronizers 5 years ago
soc_reset_tb.vhdl Exit cleanly from testbench on success 5 years ago
top-acorn-cle-215.vhdl Move alt_reset to syscon 2 years ago
top-antmicro-artix-dc-scm.vhdl Move alt_reset to syscon 2 years ago
top-arty.vhdl Arty A7: Add an option to select the number of CPU cores 3 weeks ago
top-ecpix5.vhdl ECPIX-5: Add liteeth support 10 months ago
top-generic.vhdl Remove option for "short" 16x16 bit multiplier 3 years ago
top-genesys2.vhdl Move alt_reset to syscon 2 years ago
top-nexys-video.vhdl liteeth: Regenerate from current upstream litex 10 months ago
top-orangecrab0.2.vhdl Move alt_reset to syscon 2 years ago
top-wukong-v2.vhdl liteeth: Regenerate from current upstream litex 10 months ago
wukong-v2.xdc Add support for QMTech Wukong v2 board 3 years ago