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Paul Mackerras
b595963233
This implements various improvements to the dcache with the aim of making it go faster. - We can now execute operations that don't need to access main memory (cacheable loads that hit in the cache and TLB operations) as soon as any previous operation has completed, without waiting for the state machine to become idle. - Cache line refills start with the doubleword that is needed to satisfy the load that initiated them. - Cacheable loads that miss return their data and complete as soon as the requested doubleword comes back from memory; they don't wait for the refill to finish. - We now have per-doubleword valid bits for the cache line being refilled, meaning that if a load comes in for a line that is in the process of being refilled, we can return the data and complete it within a couple of cycles of the doubleword coming in from memory. - There is now a bypass path for data being written to the cache RAM so that we can do a store hit followed immediately by a load hit to the same doubleword. This also makes the data from a refill available to load hits one cycle earlier than it would be otherwise. - Stores complete in the cycle where their wishbone operation is initiated, without waiting for the wishbone cycle to complete. - During the wishbone cycle for a store, if another store comes in that is to the same page, and we don't have a stall from the wishbone, we can send out the write for the second store in the same wishbone cycle and without going through the IDLE state first. We limit it to 7 outstanding writes that have not yet been acknowledged. - The cache tag RAM is now read on a clock edge rather than being combinatorial for reading. Its width is rounded up to a multiple of 8 bits per way so that byte enables can be used for writing individual tags. - The cache tag RAM is now written a cycle later than previously, in order to ease timing. - Data for a store hit is now written one cycle later than previously. This eases timing since we don't have to get through the tag matching and on to the write enable within a single cycle. The 2-stage bypass path means we can still handle a load hit on either of the two cycles after the store and return the correct data. (A load hit 3 or more cycles later will get the correct data from the BRAM.) - Operations can sit in r0 while there is an uncompleted operation in r1. Once the operation in r1 is completed, the operation in r0 spends one cycle in r0 for TLB/cache tag lookup and then gets put into r1.req. This can happen before r1 gets to the IDLE state. Some operations can then be completed before r1 gets to the IDLE state - a load miss to the cache line being refilled, or a store to the same page as a previous store. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
5 years ago | |
|---|---|---|
| .github/workflows | ||
| constraints | ||
| fpga | ||
| hello_world | ||
| include | ||
| lib | ||
| litedram | ||
| media | ||
| micropython | ||
| openocd | ||
| rust_lib_demo | ||
| scripts | 5 years ago | |
| sim-unisim | ||
| tests | ||
| verilator | ||
| .gitignore | ||
| LICENSE | ||
| Makefile | 5 years ago | |
| README.md | ||
| cache_ram.vhdl | ||
| common.vhdl | 5 years ago | |
| control.vhdl | 5 years ago | |
| core.vhdl | 5 years ago | |
| core_debug.vhdl | 5 years ago | |
| core_dram_tb.vhdl | ||
| core_flash_tb.vhdl | ||
| core_tb.vhdl | ||
| countzero.vhdl | ||
| countzero_tb.vhdl | ||
| cr_file.vhdl | 5 years ago | |
| cr_hazard.vhdl | 5 years ago | |
| crhelpers.vhdl | ||
| dcache.vhdl | 5 years ago | |
| dcache_tb.vhdl | ||
| decode1.vhdl | 5 years ago | |
| decode2.vhdl | 5 years ago | |
| decode_types.vhdl | ||
| divider.vhdl | ||
| divider_tb.vhdl | ||
| dmi_dtm_dummy.vhdl | ||
| dmi_dtm_tb.vhdl | ||
| dmi_dtm_xilinx.vhdl | ||
| dram_tb.vhdl | ||
| execute1.vhdl | 5 years ago | |
| fetch1.vhdl | 5 years ago | |
| glibc_random.vhdl | ||
| glibc_random_helpers.vhdl | ||
| gpr_hazard.vhdl | 5 years ago | |
| helpers.vhdl | ||
| icache.vhdl | 5 years ago | |
| icache_tb.vhdl | 5 years ago | |
| icache_test.bin | ||
| insn_helpers.vhdl | ||
| loadstore1.vhdl | 5 years ago | |
| logical.vhdl | ||
| microwatt.core | 5 years ago | |
| mmu.vhdl | ||
| multiply.vhdl | 5 years ago | |
| multiply_tb.vhdl | 5 years ago | |
| plru.vhdl | ||
| plru_tb.vhdl | ||
| ppc_fx_insns.vhdl | ||
| register_file.vhdl | 5 years ago | |
| rotator.vhdl | ||
| rotator_tb.vhdl | ||
| sim_bram.vhdl | ||
| sim_bram_helpers.vhdl | ||
| sim_bram_helpers_c.c | ||
| sim_console.vhdl | ||
| sim_console_c.c | ||
| sim_jtag.vhdl | ||
| sim_jtag_socket.vhdl | ||
| sim_jtag_socket_c.c | ||
| sim_no_flash.vhdl | ||
| sim_uart.vhdl | ||
| sim_vhpi_c.c | ||
| sim_vhpi_c.h | ||
| soc.vhdl | ||
| spi_flash_ctrl.vhdl | ||
| spi_rxtx.vhdl | ||
| sync_fifo.vhdl | ||
| syscon.vhdl | ||
| utils.vhdl | ||
| wishbone_arbiter.vhdl | ||
| wishbone_bram_tb.bin | ||
| wishbone_bram_tb.vhdl | ||
| wishbone_bram_wrapper.vhdl | ||
| wishbone_debug_master.vhdl | ||
| wishbone_types.vhdl | ||
| writeback.vhdl | 5 years ago | |
| xics.vhdl | ||
| xilinx-mult.vhdl | 5 years ago | |
README.md
Microwatt
A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.
Simulation using ghdl
You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.
- Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../
A prebuilt micropython image is also available in the micropython/ directory.
-
Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.
If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.
-
Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
To build using Docker:
make DOCKER=1
and to build using Podman:
make PODMAN=1
- Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin
Or if you were using the pre-built image:
ln -s micropython/firmware.bin main_ram.bin
- Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null
Synthesis on Xilinx FPGAs using Vivado
-
Install Vivado (I'm using the free 2019.1 webpack edition).
-
Setup Vivado paths:
source /opt/Xilinx/Vivado/2019.1/settings64.sh
- Install FuseSoC:
pip3 install --user -U fusesoc
Fedora users can get FuseSoC package via
sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
- Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
- Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.
- To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt
Testing
- A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check
Issues
This is functional, but very simple. We still have quite a lot to do:
- There are a few instructions still to be implemented
- Need to add caches and bypassing (in progress)
- Need to add supervisor state (in progress)