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Paul Mackerras
7bc7f335f1
The CTRL register has a single bit called RUN. It has some unusual behaviours: - It can only be written via SPR number 152, which is privileged - It can only be read via SPR number 136, which is non-privileged - Reading in problem state (user mode) returns the RUN bit in bit 0, but reading in privileged state (hypervisor mode) returns the RUN bit in bits 0 and 15. - Reading SPR 152 in problem state causes a HEAI (illegal instruction) interrupt, but reading in privileged state is a no-op; this is the same as for an unimplemented SPR. The RUN bit goes to the PMU and is also plumbed out to drive a LED on the Arty board. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
1 month ago | |
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| .. | ||
| LICENSE | ||
| acorn-cle-215.xdc | ||
| antmicro_artix_dc_scm.xdc | ||
| arty_a7.xdc | ||
| clk_gen_bypass.vhd | ||
| clk_gen_ecp5.vhd | ||
| clk_gen_mcmm.vhd | ||
| clk_gen_plle2.vhd | ||
| cmod_a7-35.xdc | ||
| firmware.hex | ||
| fpga-random.vhdl | ||
| fpga-random.xdc | ||
| genesys2.xdc | ||
| hello_world.hex | ||
| main_bram.vhdl | ||
| nexys-video.xdc | ||
| nexys_a7.xdc | ||
| pp_fifo.vhd | ||
| pp_soc_uart.vhd | ||
| pp_utilities.vhd | ||
| soc_reset.vhdl | ||
| soc_reset_tb.vhdl | ||
| top-acorn-cle-215.vhdl | ||
| top-antmicro-artix-dc-scm.vhdl | ||
| top-arty.vhdl | 1 month ago | |
| top-ecpix5.vhdl | ||
| top-generic.vhdl | ||
| top-genesys2.vhdl | ||
| top-nexys-video.vhdl | ||
| top-orangecrab0.2.vhdl | ||
| top-wukong-v2.vhdl | ||
| wukong-v2.xdc | ||