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Paul Mackerras
9b184ff569
This uses the exact same gateware as the nexys video, since the DRAM connection is identical to the nexys video down to the pin assignments on the FPGA. The only minor difference is that the DRAM chip on the dc-scm is a MT41K256M16TW vs. a ...HA part on the nexys video. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> [joel: rebase and tweaks] Signed-off-by: Joel Stanley <joel@jms.id.au> |
3 years ago | |
|---|---|---|
| .. | ||
| LICENSE | ||
| acorn-cle-215.xdc | ||
| antmicro_artix_dc_scm.xdc | 3 years ago | |
| arty_a7.xdc | ||
| clk_gen_bypass.vhd | ||
| clk_gen_ecp5.vhd | 4 years ago | |
| clk_gen_mcmm.vhd | ||
| clk_gen_plle2.vhd | 4 years ago | |
| cmod_a7-35.xdc | ||
| firmware.hex | ||
| fpga-random.vhdl | ||
| fpga-random.xdc | ||
| genesys2.xdc | ||
| hello_world.hex | ||
| main_bram.vhdl | 4 years ago | |
| nexys-video.xdc | ||
| nexys_a7.xdc | ||
| pp_fifo.vhd | ||
| pp_soc_uart.vhd | ||
| pp_utilities.vhd | ||
| soc_reset.vhdl | ||
| soc_reset_tb.vhdl | ||
| top-acorn-cle-215.vhdl | 3 years ago | |
| top-antmicro-artix-dc-scm.vhdl | 3 years ago | |
| top-arty.vhdl | 3 years ago | |
| top-generic.vhdl | 3 years ago | |
| top-genesys2.vhdl | 3 years ago | |
| top-nexys-video.vhdl | 3 years ago | |
| top-orangecrab0.2.vhdl | 3 years ago | |
| top-wukong-v2.vhdl | 3 years ago | |
| wukong-v2.xdc | 4 years ago | |