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microwatt/fpga
Joel Stanley 13aa52dfa7 antmicro-artix-dc-scm: Add liteeth
As with the DRAM configuration, the DC-SCM board uses the same PHY as
the Nexys Video and works with it's generated VHDL.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2 years ago
..
LICENSE Initial import of microwatt 5 years ago
acorn-cle-215.xdc acorn: Add support for the Acorn CLE 215+ 4 years ago
antmicro_artix_dc_scm.xdc antmicro-artix-dc-scm: Add Ethernet pins 2 years ago
arty_a7.xdc Remove -add from xdc files 3 years ago
clk_gen_bypass.vhd Fix clk_gen_bypass 4 years ago
clk_gen_ecp5.vhd ECP5: Adjust PLL constants so the PLL lock indication works 2 years ago
clk_gen_mcmm.vhd Fix some whitespace issues 3 years ago
clk_gen_plle2.vhd fpga/clk_gen_plle2: Add support for 50Mhz->100Mhz 2 years ago
cmod_a7-35.xdc Remove -add from xdc files 3 years ago
firmware.hex Add a few more FPGA related files 5 years ago
fpga-random.vhdl Add random number generator and implement the darn instruction 4 years ago
fpga-random.xdc Add random number generator and implement the darn instruction 4 years ago
genesys2.xdc Remove -waveform from xdc files 3 years ago
hello_world.hex hello_world: Use new headers and frequency from syscon 4 years ago
main_bram.vhdl Rename 'do' signal to avoid verilator System Verilog warning 3 years ago
nexys-video.xdc litesdcard: Add Nexys Video support 3 years ago
nexys_a7.xdc Remove -add from xdc files 3 years ago
pp_fifo.vhd pp_fifo: Fix full fifo losing all data on simultaneous push & pop 4 years ago
pp_soc_uart.vhd uart: Remove combinational loops on ack and stall signal 4 years ago
pp_utilities.vhd Initial import of microwatt 5 years ago
soc_reset.vhdl soc_reset: Use counters, add synchronizers 4 years ago
soc_reset_tb.vhdl Exit cleanly from testbench on success 4 years ago
top-acorn-cle-215.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 2 years ago
top-antmicro-artix-dc-scm.vhdl antmicro-artix-dc-scm: Add liteeth 2 years ago
top-arty.vhdl Remove option for "short" 16x16 bit multiplier 2 years ago
top-generic.vhdl Remove option for "short" 16x16 bit multiplier 2 years ago
top-genesys2.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 2 years ago
top-nexys-video.vhdl Remove option for "short" 16x16 bit multiplier 2 years ago
top-orangecrab0.2.vhdl Remove option for "short" 16x16 bit multiplier 2 years ago
top-wukong-v2.vhdl Remove option for "short" 16x16 bit multiplier 2 years ago
wukong-v2.xdc Add support for QMTech Wukong v2 board 2 years ago