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A tiny Open POWER ISA softcore written in VHDL 2008
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Paul Mackerras 963c225955 icache: Read icache tag RAM synchronously 
This uses the next_nia provided to us by fetch1 to enable the icache
tag RAM to be read synchronously (using a clock edge), which should
enable block RAMs to be used on FPGAs rather than LUT RAM or
flip-flops.  We define a separate RAM per way to avoid any problems
with the tools trying to inference byte write enables for writing to a
single way.

Since next_nia can move on, we only get one shot at reading it the
cache tag RAM entry for the current access.  If it is a miss, then the
state machine will read the cache line from RAM, and we can consider
the access to be a hit once the state machine has brought in the
doubleword we need.  The TLB hit/miss check has been modified to check
r.store_tag rather than the tag read from the tag RAM for this case.

However, it is also possible that stall_in will be asserted for the
whole time until the cache line refill is completed.  To handle this
case, we remember (in r.stalled_hit) that we detected a hit while
stalled, and use that hit once stall_in is deasserted.  This avoids
doing an unnecesary second reload of the same cache line.  The
r.stalled_hit flag gets cleared in CLR_TAG state since that is when
cache tags can be overwritten, meaning that a previously detected hit
might no longer be valid.

There is also the case where the tag read from the tag RAM is the one
we are looking for, and is the same index as the line that is starting
to be reloaded by the state machine.  If the icache gets stalled for
long enough that the line reload finishes, it would then be possible
for the access to be detected as a hit even though the cache line has
been overwritten.  To counter this, we detect the case where the cache
tag RAM entry being read is the same as the entry being written and
set a 'tag_overwrite' flag bit to indicate that one of the tags in
cache_tags_set is no longer valid.

For snooping writes to memory, we have a second read port on the cache
tag RAM.  These tags are also read synchronously, so the logic for
clearing cache line valid bits on a snoop has been adjusted (the tag
comparisons and valid bit clearing now happen in the same cycle).

This also simplifies the expression for 'insn' by removing a
dependency on r.hit_valid, fixes the instruction value sent to the
log, and deasserts stall_out when flush_in is true.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 		8 months ago
.github/workflows syscon: Implement a register for storing git hash info 2 years ago
constraints orangecrab: add Orange Crab r0.2 target 2 years ago
fpga arty: Change shield I/O pin bus into individual signals 8 months ago
hello_world hello_world: Debug print the gitinfo syscon register 2 years ago
include Merge pull request #404 from CodeConstruct:dev/gpio-interrupt 8 months ago
lib console: Add support for the 16550 UART 4 years ago
litedram Regenerate litedram with updated sdram init 2 years ago
liteeth Regenerate litedram and liteeth 3 years ago
litesdcard litesdcard: Fix and regenerate Verilog 2 years ago
media Add title image 5 years ago
micropython tests: Add updated micropython build with 16550 support 4 years ago
openocd Merge pull request #406 from shingarov/spi-kintex 2 years ago
rust_lib_demo console: Cleanup console API 4 years ago
scripts Merge pull request #420 from paulusmack/master 8 months ago
sim-unisim Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs 5 years ago
tests tests: Add a test for prefixed instructions 10 months ago
uart16550 Bundle the uart16550 core file 2 years ago
verilator verilator: Specify top level module 3 years ago
.gitignore Ignore vunit_out in git 2 years ago
LICENSE Initial import of microwatt 5 years ago
Makefile Makefile: Remove long micropython test from check_light 8 months ago
README.md README: Add Linux on Microwatt instructions 2 years ago
cache_ram.vhdl dcache: Reduce metavalue warnings 2 years ago
common.vhdl fetch1: Streamline next NIA generation further 8 months ago
control.vhdl Track hazards explicitly for XER overflow bits 2 years ago
core.vhdl core_debug: Add support for detecting writes to a memory address 8 months ago
core_debug.vhdl core_debug: Add support for detecting writes to a memory address 8 months ago
core_dram_tb.vhdl Move alt_reset to syscon 2 years ago
core_flash_tb.vhdl Reformat testbenches 3 years ago
core_tb.vhdl Reformat testbenches 3 years ago
countbits.vhdl Allow integer instructions and load/store instructions to execute together 2 years ago
countbits_tb.vhdl Add a second execute stage to the pipeline 2 years ago
cr_file.vhdl execute1: Restructure to separate out execution of side effects 2 years ago
crhelpers.vhdl crhelpers: Constraint "crnum" integer 5 years ago
dcache.vhdl dcache: Make reading of DTLB independent of d_in.valid 8 months ago
dcache_tb.vhdl Fix dcache_tb (and add dump of victim way to dcache) 2 years ago
decode1.vhdl Improve timing of redirect_nia going from decode1 to fetch1 8 months ago
decode2.vhdl Improve timing of redirect_nia going from writeback to fetch1 8 months ago
decode_types.vhdl Improve timing of redirect_nia going from writeback to fetch1 8 months ago
divider.vhdl Add a second execute stage to the pipeline 2 years ago
divider_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 3 years ago
dmi_dtm_dummy.vhdl Fix build issue in dmi_dtm_dummy.vhdl 5 years ago
dmi_dtm_ecp5.vhdl dmi_dtm_ecp5: Use ECP5 JTAGG for DMI 2 years ago
dmi_dtm_tb.vhdl Reformat testbenches 3 years ago
dmi_dtm_xilinx.vhdl Fix some whitespace issues 3 years ago
dram_tb.vhdl Move alt_reset to syscon 2 years ago
execute1.vhdl Improve timing of redirect_nia going from writeback to fetch1 8 months ago
fetch1.vhdl fetch1: Streamline next NIA generation further 8 months ago
foreign_random.vhdl Make core testbenches recognized by VUnit 3 years ago
fpu.vhdl Change the multiplier interface to support signed multipliers 2 years ago
git.vhdl.in syscon: Implement a register for storing git hash info 2 years ago
glibc_random.vhdl Reformat glibc_random 5 years ago
glibc_random_helpers.vhdl Reformat glibc_random 5 years ago
gpio.vhdl gpio: Add interrupts and trigger registers 2 years ago
helpers.vhdl Metavalue cleanup for helpers.vhdl 2 years ago
icache.vhdl icache: Read icache tag RAM synchronously 8 months ago
icache_tb.vhdl fix: fix icache_tb not finishing correctly 2 years ago
icache_test.bin icache_tb: Improve test and include test file 5 years ago
insn_helpers.vhdl Decode prefixed instructions 10 months ago
loadstore1.vhdl Implement interrupts for prefixed instructions 10 months ago
logical.vhdl Implement byte reversal instructions 8 months ago
microwatt.core Merge pull request #415 from ozbenh/uart16550-core 2 years ago
mmu.vhdl Metavalue cleanup for mmu.vhdl 2 years ago
multiply-32s.vhdl Change the multiplier interface to support signed multipliers 2 years ago
multiply.vhdl Change the multiplier interface to support signed multipliers 2 years ago
multiply_tb.vhdl multiply_tb: Fix multiply_tb.vhdl for the new multiplier interface 2 years ago
nonrandom.vhdl Add random number generator and implement the darn instruction 4 years ago
plru_tb.vhdl Fix plru_tb to use the new plrufn and take out the old plru.vhdl 2 years ago
plrufn.vhdl icache: Split PLRU into storage and logic 2 years ago
pmu.vhdl Metavalue cleanup for pmu.vhdl 2 years ago
ppc_fx_insns.vhdl Fix some whitespace issues 3 years ago
predecode.vhdl Improve timing of redirect_nia going from writeback to fetch1 8 months ago
random.vhdl Make core testbenches recognized by VUnit 3 years ago
register_file.vhdl Metavalue cleanup for register_file.vhdl 2 years ago
rotator.vhdl Metavalue cleanup for rotator.vhdl 2 years ago
rotator_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 3 years ago
run.py Add vhdl_ls.toml dump to run.py 1 year ago
sim_16550_uart.vhdl uart: Add a simulation model for the 16550 compatible UART 4 years ago
sim_bram.vhdl Rename 'do' signal to avoid verilator System Verilog warning 3 years ago
sim_bram_helpers.vhdl ram: Rework main RAM interface 5 years ago
sim_bram_helpers_c.c Consolidate VHPI code 4 years ago
sim_console.vhdl Reformat sim_console 5 years ago
sim_console_c.c sim_console: Fix polling to check for POLLIN 4 years ago
sim_jtag.vhdl Add jtag support in simulation via a socket 5 years ago
sim_jtag_socket.vhdl Add jtag support in simulation via a socket 5 years ago
sim_jtag_socket_c.c Consolidate VHPI code 4 years ago
sim_no_flash.vhdl spi: Add simulation support 4 years ago
sim_pp_uart.vhdl uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl 4 years ago
sim_vhpi_c.c Consolidate VHPI code 4 years ago
sim_vhpi_c.h Consolidate VHPI code 4 years ago
soc.vhdl Merge pull request #409 from CodeConstruct/dev/soc-reset 1 year ago
spi_flash_ctrl.vhdl Remove some FPGA style signal inits 2 years ago
spi_rxtx.vhdl Remove some FPGA style signal inits 2 years ago
sync_fifo.vhdl litedram: Add an L2 cache with store queue 4 years ago
syscon.vhdl Move alt_reset to syscon 2 years ago
utils.vhdl litedram: Add support for booting without BRAM 4 years ago
wishbone_arbiter.vhdl wb_arbiter: Early master selection 5 years ago
wishbone_bram_tb.bin ram: Rework main RAM interface 5 years ago
wishbone_bram_tb.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
wishbone_bram_wrapper.vhdl wishbone_bram_wrapper ram_addr_bits is 1 bit off 2 years ago
wishbone_debug_master.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
wishbone_types.vhdl Introduce addr_to_wb() and wb_to_addr() helpers 3 years ago
writeback.vhdl fetch1: Streamline next NIA generation further 8 months ago
xics.vhdl xics: Fix -Whide warnings 2 years ago
xilinx-mult-32s.vhdl Change the multiplier interface to support signed multipliers 2 years ago
xilinx-mult.vhdl Change the multiplier interface to support signed multipliers 2 years ago

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • If this is your first time using fusesoc, initialize fusesoc. This is needed to be able to pull down fussoc library components referenced by microwatt. Run
fusesoc init
fusesoc fetch uart16550
fusesoc library add microwatt /path/to/microwatt
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100): You may wish to ensure you have installed Digilent Board files or appropriate files for your board first.
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Linux on Microwatt

Mainline Linux supports Microwatt as of v5.14. The Arty A7 is the best tested platform, but it's also been tested on the OrangeCrab and ButterStick.

  1. Use buildroot to create a userspace

    A small change is required to glibc in order to support the VMX/AltiVec-less Microwatt, as float128 support is mandiatory and for this in GCC requires VSX/AltiVec. This change is included in Joel's buildroot fork, along with a defconfig:

    git clone -b microwatt https://github.com/shenki/buildroot
cd buildroot
make ppc64le_microwatt_defconfig
make

    The output is output/images/rootfs.cpio.

  2. Build the Linux kernel

    git clone https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
cd linux
make ARCH=powerpc microwatt_defconfig
make ARCH=powerpc CROSS_COMPILE=powerpc64le-linux-gnu- \
  CONFIG_INITRAMFS_SOURCE=/buildroot/output/images/rootfs.cpio -j`nproc`

    The output is arch/powerpc/boot/dtbImage.microwatt.elf.

  3. Build gateware using FuseSoC

    First configure FuseSoC as above.

    fusesoc run --build --target=arty_a7-100 microwatt --no_bram --memory_size=0

    The output is build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit.

  4. Program the flash

    This operation will overwrite the contents of your flash.

    For the Arty A7 A100, set FLASH_ADDRESS to 0x400000 and pass -f a100.

    For the Arty A7 A35, set FLASH_ADDRESS to 0x300000 and pass -f a35.

    microwatt/openocd/flash-arty -f a100 build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit
microwatt/openocd/flash-arty -f a100 dtbImage.microwatt.elf -t bin -a $FLASH_ADDRESS

  5. Connect to the second USB TTY device exposed by the FPGA

    minicom -D /dev/ttyUSB1

    The gateware has firmware that will look at FLASH_ADDRESS and attempt to parse an ELF there, loading it to the address specified in the ELF header and jumping to it.

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

  • There are a few instructions still to be implemented:
    • Vector/VMX/VSX