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Make the shield I/O pins be individual signals rather than a bus in order to avoid warnings on pins which don't have both a driver and a receiver. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
12 months ago | |
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LICENSE | 5 years ago | |
acorn-cle-215.xdc | 4 years ago | |
antmicro_artix_dc_scm.xdc | 2 years ago | |
arty_a7.xdc | 12 months ago | |
clk_gen_bypass.vhd | 5 years ago | |
clk_gen_ecp5.vhd | 3 years ago | |
clk_gen_mcmm.vhd | 3 years ago | |
clk_gen_plle2.vhd | 3 years ago | |
cmod_a7-35.xdc | 3 years ago | |
firmware.hex | 5 years ago | |
fpga-random.vhdl | 4 years ago | |
fpga-random.xdc | 4 years ago | |
genesys2.xdc | 3 years ago | |
hello_world.hex | 4 years ago | |
main_bram.vhdl | 3 years ago | |
nexys-video.xdc | 3 years ago | |
nexys_a7.xdc | 3 years ago | |
pp_fifo.vhd | 4 years ago | |
pp_soc_uart.vhd | 4 years ago | |
pp_utilities.vhd | 5 years ago | |
soc_reset.vhdl | 4 years ago | |
soc_reset_tb.vhdl | 4 years ago | |
top-acorn-cle-215.vhdl | 2 years ago | |
top-antmicro-artix-dc-scm.vhdl | 2 years ago | |
top-arty.vhdl | 12 months ago | |
top-generic.vhdl | 2 years ago | |
top-genesys2.vhdl | 2 years ago | |
top-nexys-video.vhdl | 2 years ago | |
top-orangecrab0.2.vhdl | 2 years ago | |
top-wukong-v2.vhdl | 2 years ago | |
wukong-v2.xdc | 3 years ago |