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478b787c10
The VUnit log package is a SW style logging framework in VHDL and the check package is an assertion library doing its error reporting with VUnit logging. These testbenches don't use, and do not need, very advanced logging/checking features but the following was possible to improve - Checking equality in VHDL can be quite tedious with a lot of type conversions and long message strings to explain the data received and what was expected. VUnit's check_equal procedure allow comparison between same or similar types and automatically create the error message for you. - The code has report statements used for testbench progress reporting and debugging. These were replaced with the info and debug procedures. info logs are visible by default while debug is not. This means that debug logs don't have to be commented, which they are now, when not used. Instead there is a show procedure making debug messages visible. The show procedure has been commented to hide the debug messages but a more elegant solution is to control visibility from a generic and then set that generic from the command line. I've left this as a TODO but the run script allow you to extend the standard CLI of VUnit to add new options and you can also set generics from the run script. - VUnit log messages are color coded if color codes are supported by the terminal. It makes it quicker to spot messages of different types when there are many log messages. Error messages will always be made visible on the terminal but you must use the -v (verbose) to see other logs. - Some tests have a lot of "metvalue detected" warning messages from the numeric_std package and these clutter the logs when using the -v option. VUnit has a simulator independent option allowing you to suppress those messages. That option has been enabled. Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com> |
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| .github/workflows | 4 years ago | |
| constraints | 5 years ago | |
| fpga | 4 years ago | |
| hello_world | 4 years ago | |
| include | 4 years ago | |
| lib | 5 years ago | |
| litedram | 4 years ago | |
| liteeth | 5 years ago | |
| litesdcard | 4 years ago | |
| media | 5 years ago | |
| micropython | 5 years ago | |
| openocd | 4 years ago | |
| rust_lib_demo | 5 years ago | |
| scripts | 4 years ago | |
| sim-unisim | 5 years ago | |
| tests | 4 years ago | |
| uart16550 | 5 years ago | |
| verilator | 5 years ago | |
| .gitignore | 5 years ago | |
| LICENSE | 5 years ago | |
| Makefile | 4 years ago | |
| README.md | 4 years ago | |
| cache_ram.vhdl | 4 years ago | |
| common.vhdl | 4 years ago | |
| control.vhdl | 4 years ago | |
| core.vhdl | 4 years ago | |
| core_debug.vhdl | 4 years ago | |
| core_dram_tb.vhdl | 4 years ago | |
| core_flash_tb.vhdl | 4 years ago | |
| core_tb.vhdl | 4 years ago | |
| countzero.vhdl | 4 years ago | |
| countzero_tb.vhdl | 4 years ago | |
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| dcache.vhdl | 4 years ago | |
| dcache_tb.vhdl | 4 years ago | |
| decode1.vhdl | 4 years ago | |
| decode2.vhdl | 4 years ago | |
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| divider.vhdl | 4 years ago | |
| divider_tb.vhdl | 4 years ago | |
| dmi_dtm_dummy.vhdl | 5 years ago | |
| dmi_dtm_tb.vhdl | 4 years ago | |
| dmi_dtm_xilinx.vhdl | 4 years ago | |
| dram_tb.vhdl | 4 years ago | |
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| icache_tb.vhdl | 4 years ago | |
| icache_test.bin | 5 years ago | |
| insn_helpers.vhdl | 4 years ago | |
| loadstore1.vhdl | 4 years ago | |
| logical.vhdl | 4 years ago | |
| microwatt.core | 4 years ago | |
| mmu.vhdl | 4 years ago | |
| multiply.vhdl | 4 years ago | |
| multiply_tb.vhdl | 4 years ago | |
| nonrandom.vhdl | 4 years ago | |
| plru.vhdl | 4 years ago | |
| plru_tb.vhdl | 4 years ago | |
| ppc_fx_insns.vhdl | 4 years ago | |
| random.vhdl | 4 years ago | |
| register_file.vhdl | 4 years ago | |
| rotator.vhdl | 4 years ago | |
| rotator_tb.vhdl | 4 years ago | |
| run.py | 4 years ago | |
| sim_16550_uart.vhdl | 5 years ago | |
| sim_bram.vhdl | 5 years ago | |
| sim_bram_helpers.vhdl | 5 years ago | |
| sim_bram_helpers_c.c | 5 years ago | |
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| sim_console_c.c | 5 years ago | |
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| sim_jtag_socket.vhdl | 5 years ago | |
| sim_jtag_socket_c.c | 5 years ago | |
| sim_no_flash.vhdl | 5 years ago | |
| sim_pp_uart.vhdl | 5 years ago | |
| sim_vhpi_c.c | 5 years ago | |
| sim_vhpi_c.h | 5 years ago | |
| soc.vhdl | 4 years ago | |
| spi_flash_ctrl.vhdl | 4 years ago | |
| spi_rxtx.vhdl | 4 years ago | |
| sync_fifo.vhdl | 5 years ago | |
| syscon.vhdl | 4 years ago | |
| utils.vhdl | 5 years ago | |
| wishbone_arbiter.vhdl | 5 years ago | |
| wishbone_bram_tb.bin | 5 years ago | |
| wishbone_bram_tb.vhdl | 4 years ago | |
| wishbone_bram_wrapper.vhdl | 5 years ago | |
| wishbone_debug_master.vhdl | 5 years ago | |
| wishbone_types.vhdl | 4 years ago | |
| writeback.vhdl | 4 years ago | |
| xics.vhdl | 5 years ago | |
| xilinx-mult.vhdl | 4 years ago | |
README.md
Microwatt
A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.
Simulation using ghdl
You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.
- Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../
A prebuilt micropython image is also available in the micropython/ directory.
-
Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.
If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.
-
Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
To build using Docker:
make DOCKER=1
and to build using Podman:
make PODMAN=1
- Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin
Or if you were using the pre-built image:
ln -s micropython/firmware.bin main_ram.bin
- Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null
Synthesis on Xilinx FPGAs using Vivado
-
Install Vivado (I'm using the free 2019.1 webpack edition).
-
Setup Vivado paths:
source /opt/Xilinx/Vivado/2019.1/settings64.sh
- Install FuseSoC:
pip3 install --user -U fusesoc
Fedora users can get FuseSoC package via
sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
- If this is your first time using fusesoc, initialize fusesoc. This is needed to be able to pull down fussoc library components referenced by microwatt. Run
fusesoc init
- Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
- Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100): You may wish to ensure you have installed Digilent Board files or appropriate files for your board first.
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.
- To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt
Testing
- A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check
Issues
This is functional, but very simple. We still have quite a lot to do:
- There are a few instructions still to be implemented
- Need to add caches and bypassing (in progress)
- Need to add supervisor state (in progress)