Paul Mackerras
3eb07dc637
This is required by the architecture. It means that the error bits reported in DSISR or SRR1 now come from the permission/RC check done on the refetched PTE rather than the TLB entry. Unfortunately that somewhat breaks the software-loaded TLB mode of operation in that DSISR/SRR1 always report no PTE rather than permission error or RC failure. This also restructures the loadstore1 state machine a bit, combining the FIRST_ACK_WAIT and LAST_ACK_WAIT states into a single state and the MMU_LOOKUP_1ST and MMU_LOOKUP_LAST states likewise. We now have a 'dwords_done' bit to say whether the first transfer of two (for an unaligned access) has been done. The cache paradox error (where a non-cacheable access finds a hit in the cache) is now the only cause of DSI from the dcache. This should probably be a machine check rather than DSI in fact. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
5 years ago | |
|---|---|---|
| constraints | ||
| fpga | ||
| hello_world | 5 years ago | |
| media | ||
| micropython | ||
| openocd | ||
| rust_lib_demo | 5 years ago | |
| scripts | 5 years ago | |
| sim-unisim | ||
| tests | 5 years ago | |
| .gitignore | ||
| .travis.yml | ||
| LICENSE | ||
| Makefile | 5 years ago | |
| Makefile.synth | ||
| README.md | 5 years ago | |
| cache_ram.vhdl | ||
| common.vhdl | 5 years ago | |
| control.vhdl | ||
| core.vhdl | 5 years ago | |
| core_debug.vhdl | 5 years ago | |
| core_tb.vhdl | ||
| countzero.vhdl | ||
| countzero_tb.vhdl | ||
| cr_file.vhdl | ||
| cr_hazard.vhdl | ||
| crhelpers.vhdl | ||
| dcache.vhdl | 5 years ago | |
| dcache_tb.vhdl | 5 years ago | |
| decode1.vhdl | 5 years ago | |
| decode2.vhdl | 5 years ago | |
| decode_types.vhdl | 5 years ago | |
| divider.vhdl | ||
| divider_tb.vhdl | ||
| dmi_dtm_dummy.vhdl | ||
| dmi_dtm_tb.vhdl | ||
| dmi_dtm_xilinx.vhdl | ||
| execute1.vhdl | 5 years ago | |
| fetch1.vhdl | ||
| fetch2.vhdl | ||
| glibc_random.vhdl | ||
| glibc_random_helpers.vhdl | ||
| gpr_hazard.vhdl | ||
| helpers.vhdl | ||
| icache.vhdl | ||
| icache_tb.vhdl | ||
| icache_test.bin | ||
| insn_helpers.vhdl | ||
| loadstore1.vhdl | 5 years ago | |
| logical.vhdl | ||
| microwatt.core | 5 years ago | |
| mmu.vhdl | 5 years ago | |
| multiply.vhdl | ||
| multiply_tb.vhdl | ||
| plru.vhdl | ||
| plru_tb.vhdl | ||
| ppc_fx_insns.vhdl | ||
| register_file.vhdl | 5 years ago | |
| rotator.vhdl | 5 years ago | |
| rotator_tb.vhdl | 5 years ago | |
| sim_bram.vhdl | ||
| sim_bram_helpers.vhdl | ||
| sim_bram_helpers_c.c | ||
| sim_console.vhdl | ||
| sim_console_c.c | ||
| sim_jtag.vhdl | ||
| sim_jtag_socket.vhdl | ||
| sim_jtag_socket_c.c | ||
| sim_uart.vhdl | ||
| sim_vhpi_c.c | ||
| sim_vhpi_c.h | ||
| soc.vhdl | ||
| utils.vhdl | ||
| wishbone_arbiter.vhdl | ||
| wishbone_bram_tb.bin | ||
| wishbone_bram_tb.vhdl | ||
| wishbone_bram_wrapper.vhdl | ||
| wishbone_debug_master.vhdl | 5 years ago | |
| wishbone_types.vhdl | ||
| writeback.vhdl | ||
| xics.vhdl | ||
README.md
Microwatt
A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.
Simulation using ghdl
You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.
- Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../
A prebuilt micropython image is also available in the micropython/ directory.
-
Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.
If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or podman images. Read through the Makefile for details.
-
Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
- Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin
Or if you were using the pre-built image:
ln -s micropython/firmware.bin main_ram.bin
- Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null
Synthesis on Xilinx FPGAs using Vivado
-
Install Vivado (I'm using the free 2019.1 webpack edition).
-
Setup Vivado paths:
source /opt/Xilinx/Vivado/2019.1/settings64.sh
- Install FuseSoC:
pip3 install --user -U fusesoc
Fedora users can get FuseSoC package via
sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
- Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
- Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.
- To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt
Testing
- A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check
Issues
This is functional, but very simple. We still have quite a lot to do:
- There are a few instructions still to be implemented
- Need to add caches and bypassing (in progress)
- Need to add supervisor state (in progress)