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microwatt/fpga
Paul Mackerras d1e8e62fee Remove option for "short" 16x16 bit multiplier
Now that we have a 33 bit x 33 bit signed multiplier in execute1,
there is really no need for the 16 bit multiplier.  The coremark
results are just as good without it as with it.  This removes the
option for the sake of simplicity.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
..
LICENSE
acorn-cle-215.xdc acorn: Add support for the Acorn CLE 215+ 4 years ago
arty_a7.xdc Remove -add from xdc files 3 years ago
clk_gen_bypass.vhd
clk_gen_ecp5.vhd ECP5: Adjust PLL constants so the PLL lock indication works 3 years ago
clk_gen_mcmm.vhd Fix some whitespace issues 3 years ago
clk_gen_plle2.vhd fpga/clk_gen_plle2: Add support for 50Mhz->100Mhz 3 years ago
cmod_a7-35.xdc Remove -add from xdc files 3 years ago
firmware.hex
fpga-random.vhdl Add random number generator and implement the darn instruction 4 years ago
fpga-random.xdc Add random number generator and implement the darn instruction 4 years ago
genesys2.xdc Remove -waveform from xdc files 3 years ago
hello_world.hex
main_bram.vhdl Rename 'do' signal to avoid verilator System Verilog warning 3 years ago
nexys-video.xdc litesdcard: Add Nexys Video support 3 years ago
nexys_a7.xdc Remove -add from xdc files 3 years ago
pp_fifo.vhd
pp_soc_uart.vhd
pp_utilities.vhd
soc_reset.vhdl
soc_reset_tb.vhdl
top-acorn-cle-215.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 2 years ago
top-arty.vhdl Remove option for "short" 16x16 bit multiplier 2 years ago
top-generic.vhdl Remove option for "short" 16x16 bit multiplier 2 years ago
top-genesys2.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 2 years ago
top-nexys-video.vhdl Remove option for "short" 16x16 bit multiplier 2 years ago
top-orangecrab0.2.vhdl Remove option for "short" 16x16 bit multiplier 2 years ago
top-wukong-v2.vhdl Remove option for "short" 16x16 bit multiplier 2 years ago
wukong-v2.xdc Add support for QMTech Wukong v2 board 3 years ago