microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

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Benjamin Herrenschmidt 0f97b320f6 Change default frequency to 100Mhz LiteDRAM at the moment pretty much enforces 100Mhz, and our software isn't quite yet adaptable, so switch out default to 100Mhz accross the board. Recent timing improvements should make it a non-issue. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 years ago
constraints	Initial support for ghdl synthesis	5 years ago
fpga	Add a few FFs on the RX input to avoid metastability issues	5 years ago
hello_world	Merge remote-tracking branch 'remotes/origin/master'	5 years ago
media	…
micropython	Update micropython	5 years ago
openocd	Initial support for ghdl synthesis	5 years ago
rust_lib_demo	Merge remote-tracking branch 'remotes/origin/master'	5 years ago
scripts	Add VHDL TAGS	5 years ago
sim-unisim	…
tests	Merge remote-tracking branch 'remotes/origin/master'	5 years ago
.gitignore	Add VHDL TAGS	5 years ago
.travis.yml	…
LICENSE	…
Makefile	Merge remote-tracking branch 'remotes/origin/master'	5 years ago
Makefile.synth	make the sources volume mount SELinux friendly	5 years ago
README.md	Change the default cross compiler prefix to powerpc64le-linux-gnu-	5 years ago
cache_ram.vhdl	…
common.vhdl	Merge remote-tracking branch 'remotes/origin/master'	5 years ago
control.vhdl	execute: Implement bypass from output of execute1 to input	5 years ago
core.vhdl	XICS interrupt controller	5 years ago
core_debug.vhdl	…
core_tb.vhdl	Reduce simulated and default FPGA RAM to 384kB	5 years ago
countzero.vhdl	countzero: Add a register to help make timing	5 years ago
countzero_tb.vhdl	countzero: Add a register to help make timing	5 years ago
cr_file.vhdl	Dump CTR, LR and CR on sim termination, and update our tests	5 years ago
cr_hazard.vhdl	sprs: Store common SPRs in register file	5 years ago
crhelpers.vhdl	…
dcache.vhdl	dcache: Don't assert on dcbz cache hit	5 years ago
dcache_tb.vhdl	loadstore1: Move logic from dcache to loadstore1	5 years ago
decode1.vhdl	dcache: Implement the dcbz instruction	5 years ago
decode2.vhdl	Plumb insn_type through to loadstore1	5 years ago
decode_types.vhdl	Remove sim_config instruction	5 years ago
divider.vhdl	execute1: Remember dest GPR, RC, OE, XER for slow operations	5 years ago
divider_tb.vhdl	execute1: Remember dest GPR, RC, OE, XER for slow operations	5 years ago
dmi_dtm_dummy.vhdl	…
dmi_dtm_tb.vhdl	…
dmi_dtm_xilinx.vhdl	…
execute1.vhdl	execute1: Fix interrupt delivery during slow instructions	5 years ago
fetch1.vhdl	…
fetch2.vhdl	…
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
gpr_hazard.vhdl	execute: Implement bypass from output of execute1 to input	5 years ago
helpers.vhdl	…
icache.vhdl	Fix a ghdlsynth issue in icache	5 years ago
icache_tb.vhdl	…
icache_test.bin	…
insn_helpers.vhdl	Implement CRNOR and friends	5 years ago
loadstore1.vhdl	dcache: Implement the dcbz instruction	5 years ago
logical.vhdl	execute: Move popcnt and prty instructions into the logical unit	5 years ago
microwatt.core	Change default frequency to 100Mhz	5 years ago
multiply.vhdl	execute1: Remember dest GPR, RC, OE, XER for slow operations	5 years ago
multiply_tb.vhdl	execute1: Remember dest GPR, RC, OE, XER for slow operations	5 years ago
plru.vhdl	…
plru_tb.vhdl	…
ppc_fx_insns.vhdl	sprs: Store common SPRs in register file	5 years ago
register_file.vhdl	Fix ghdlsynth issue in register file	5 years ago
rotator.vhdl	…
rotator_tb.vhdl	…
sim_bram.vhdl	…
sim_bram_helpers.vhdl	…
sim_bram_helpers_c.c	Consolidate VHPI code	5 years ago
sim_console.vhdl	…
sim_console_c.c	Consolidate VHPI code	5 years ago
sim_jtag.vhdl	…
sim_jtag_socket.vhdl	…
sim_jtag_socket_c.c	Consolidate VHPI code	5 years ago
sim_uart.vhdl	Wire up sim uart TX interrupt	5 years ago
sim_vhpi_c.c	Consolidate VHPI code	5 years ago
sim_vhpi_c.h	Consolidate VHPI code	5 years ago
soc.vhdl	XICS interrupt controller	5 years ago
utils.vhdl	Add log2ceil and use it in bram code	5 years ago
wishbone_arbiter.vhdl	…
wishbone_bram_tb.bin	…
wishbone_bram_tb.vhdl	…
wishbone_bram_wrapper.vhdl	Add log2ceil and use it in bram code	5 years ago
wishbone_debug_master.vhdl	wishbone_debug_master: Fix address auto-increment for memory writes	5 years ago
wishbone_types.vhdl	…
writeback.vhdl	execute1: Simplify the interrupt logic a little	5 years ago
xics.vhdl	XICS interrupt controller	5 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.

git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or podman images. Read through the Makefile for details.
Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):

fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)