A tiny Open POWER ISA softcore written in VHDL 2008
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Anton Blanchard 06266fe84a Orange Crab is 48MHz not 50MHz, bump PLL frequency
I'm not sure why I set the input frequency for the Orange Crab to 50MHz.
Since we easily make timing now, bump our output frequency to 48MHz as
well.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
.github/workflows ci: Add verilator tests 3 years ago
constraints
fpga core: Add a short multiplier 3 years ago
hello_world
include
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litedram litedram: Regenerate from upstream litex 3 years ago
liteeth liteeth: Regenerate from upstream litex 3 years ago
litesdcard litesdcard: Use vendor not board type 3 years ago
media
micropython
openocd openocd: Fix verify command for v0.10 3 years ago
rust_lib_demo
scripts makefile: Add some verilator micropython tests 3 years ago
sim-unisim
tests tests/misc: Add a test for a load that hits two preceding stores 3 years ago
uart16550
verilator verilator: Specify top level module 3 years ago
.gitignore
LICENSE
Makefile Orange Crab is 48MHz not 50MHz, bump PLL frequency 3 years ago
README.md
cache_ram.vhdl
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control.vhdl
core.vhdl core: Add a short multiplier 3 years ago
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core_dram_tb.vhdl
core_flash_tb.vhdl
core_tb.vhdl
countzero.vhdl
countzero_tb.vhdl
cr_file.vhdl
crhelpers.vhdl
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dcache_tb.vhdl
decode1.vhdl Merge pull request #324 from paulusmack/master 3 years ago
decode2.vhdl
decode_types.vhdl
divider.vhdl
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dmi_dtm_dummy.vhdl
dmi_dtm_tb.vhdl
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fpu.vhdl
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gpio.vhdl
helpers.vhdl
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icache_tb.vhdl
icache_test.bin
insn_helpers.vhdl
loadstore1.vhdl loadstore1: Make r1.req.addr not depend on l_in.valid 3 years ago
logical.vhdl core: Fix mcrxrx, addpcis and bpermd 3 years ago
microwatt.core core: Add a short multiplier 3 years ago
mmu.vhdl
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multiply_tb.vhdl
nonrandom.vhdl
plru.vhdl
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sim_console.vhdl
sim_console_c.c
sim_jtag.vhdl
sim_jtag_socket.vhdl
sim_jtag_socket_c.c
sim_no_flash.vhdl
sim_pp_uart.vhdl
sim_vhpi_c.c
sim_vhpi_c.h
soc.vhdl core: Add a short multiplier 3 years ago
spi_flash_ctrl.vhdl
spi_rxtx.vhdl
sync_fifo.vhdl
syscon.vhdl
utils.vhdl
wishbone_arbiter.vhdl
wishbone_bram_tb.bin
wishbone_bram_tb.vhdl
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wishbone_types.vhdl
writeback.vhdl PMU: Add several more events 3 years ago
xics.vhdl Fix some whitespace issues 3 years ago
xilinx-mult.vhdl core: Add a short multiplier 3 years ago

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • If this is your first time using fusesoc, initialize fusesoc. This is needed to be able to pull down fussoc library components referenced by microwatt. Run
fusesoc init
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100): You may wish to ensure you have installed Digilent Board files or appropriate files for your board first.
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)