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f5ca58b3c4

Merge pull request #123 from antonblanchard/spi-conf Anton Blanchard 2019-12-09 20:35:24 +1100
20674e0d65 Add SPI configuration to Xilinx constraint files #123 Anton Blanchard 2019-12-09 16:12:37 +1100
23ade0b1c3 decode2: Minor cleanup #122 Paul Mackerras 2019-12-05 12:42:31 +1100
e4f475e17f sprs: Store common SPRs in register file Benjamin Herrenschmidt 2019-10-31 13:48:43 +1100
afdd593502 spr: Add translation from SPR to special GPR number Benjamin Herrenschmidt 2019-10-31 12:09:14 +1100
5a0458dec1 divider: Fix overflow calculation Paul Mackerras 2019-12-07 15:26:25 +1100
d04887fdcd decode1: Add OE=1 forms of add/sub, mul and div instructions Paul Mackerras 2019-12-06 08:25:28 +1100
ec9b27660f execute: Copy XER[SO] to CR for cmp[i] and cmpl[i] instructions Paul Mackerras 2019-12-07 14:31:33 +1100
501b6daf9b Add basic XER support Benjamin Herrenschmidt 2019-10-30 13:53:23 +1100
f291efa266 decode1: Mark ALU ops using carry as pipelined Benjamin Herrenschmidt 2019-11-14 15:25:28 +1100
1249a11349 cr_file: Check write_cr_enable Benjamin Herrenschmidt 2019-10-30 13:26:43 +1100
73eb6a0ffd decode2: Minor cleanup #121 Paul Mackerras 2019-12-05 12:42:31 +1100
d9cde63bbc divide: Move data formatting out of decode2 Paul Mackerras 2019-12-05 12:41:23 +1100
9568e5f848 multiply: Move data formatting out of decode2 Paul Mackerras 2019-12-05 09:32:13 +1100
ac7df6fc04

Merge pull request #120 from antonblanchard/spr-decode-cleanup Anton Blanchard 2019-11-18 14:07:16 +1100
726e4db66a

Merge pull request #119 from antonblanchard/reduce-pipe-depth Anton Blanchard 2019-11-18 14:05:48 +1100
9b1394e236

Merge pull request #118 from antonblanchard/bus-pipeline Anton Blanchard 2019-11-15 16:02:57 +1100
98bd8b73c0 control: Reduce pipeline depth to 1 #119 Benjamin Herrenschmidt 2019-10-31 19:43:58 +1100
83a8bb0238 spr: Cleanup decoding of SPR numbers #120 Benjamin Herrenschmidt 2019-10-31 11:42:10 +1100
cff4b13a9b wb_arbiter: Early master selection #118 Benjamin Herrenschmidt 2019-10-23 15:06:39 +1100
4145ff4d98 Add Blinky sample #117 Alastair D'Silva 2019-10-29 15:25:59 +1100
45f502112a Add GPIO for Arty A7 Alastair D'Silva 2019-10-29 15:56:38 +1100
716ff6d8c4 Add Blinky sample #116 Alastair D'Silva 2019-10-29 15:25:59 +1100
5a1e065056 Add GPIO for Arty A7 Alastair D'Silva 2019-10-29 15:56:38 +1100
bc2acfde2f wb_arbiter: Make arbiter size parametric Benjamin Herrenschmidt 2019-10-23 14:28:12 +1100
472d8f94a2 wb_arbiter: Avoid IDLE cycle when not changing master Benjamin Herrenschmidt 2019-10-23 14:01:48 +1100
336f0e0690 ram: Ack stores early Benjamin Herrenschmidt 2019-10-23 14:00:30 +1100
8e0389b973 ram: Rework main RAM interface Benjamin Herrenschmidt 2019-10-23 12:08:55 +1100
9a63c098a5 Move log2/ispow2 to a utils package Benjamin Herrenschmidt 2019-10-23 10:52:37 +1100
3349bdc798 ram: Add block RAM pipelining Benjamin Herrenschmidt 2019-10-22 16:05:18 +1100
797b1bb045 decode: Reformat decode_types.vhdl Benjamin Herrenschmidt 2019-10-21 22:57:51 +1100
d2762e70e5 Add option to not flatten hierarchy Benjamin Herrenschmidt 2019-10-21 15:15:07 +1100
48f260761b writeback: Slightly improve timing Benjamin Herrenschmidt 2019-10-21 15:11:47 +1100
365f60b693 simple_ram: Turn on pipelining Benjamin Herrenschmidt 2019-10-19 10:34:48 +1100
c22734d0d9 wb_debug: Add wishbone pipelining support Benjamin Herrenschmidt 2019-10-19 10:33:31 +1100
3df018cdc0 icache: Add wishbone pipelining support Benjamin Herrenschmidt 2019-10-19 10:33:04 +1100
d363daa692 dcache: Add wishbone pipelining support Benjamin Herrenschmidt 2019-10-19 10:32:46 +1100
e638c3e8ae fpga/bram: Generate stall signal Benjamin Herrenschmidt 2019-10-19 21:22:33 +1100
37acb35773 simple_ram: Add pipelining support Benjamin Herrenschmidt 2019-10-19 10:30:39 +1100
df1a9237f6 intercon: Generate stall signals for non-pipelined slaves Benjamin Herrenschmidt 2019-10-19 10:27:56 +1100
7a4a9b6377 wb_arbiter: Forward stall signals Benjamin Herrenschmidt 2019-10-19 10:27:02 +1100
b1424e859e icache_tb: Initialize stop_mark Benjamin Herrenschmidt 2019-10-19 10:26:09 +1100
79101041d6 wishbone: Add stall signal Benjamin Herrenschmidt 2019-10-17 20:07:18 +1100
559b3bcf2d pp_uart: reformat Benjamin Herrenschmidt 2019-10-19 09:21:42 +1100
9620a76281

Merge pull request #115 from antonblanchard/reduce-wishbone Anton Blanchard 2019-10-25 17:10:01 +1100
247d7d4aa0

Merge pull request #113 from mikey/exec-sim-remove Anton Blanchard 2019-10-25 15:52:24 +1100
1b6c246379

Merge pull request #114 from antonblanchard/dcache Anton Blanchard 2019-10-25 15:49:33 +1100
bd4ac06243 Remove SIM generic from execute1 #113 Michael Neuling 2019-10-24 17:07:58 +1100
6dd0b514ac Reduce wishbone address size to 32-bit #115 Benjamin Herrenschmidt 2019-10-17 10:21:41 +1100
1a63c39704 Make it possible to change wishbone address size Benjamin Herrenschmidt 2019-09-25 16:54:25 +1000
cb4451498f dcache: Add testbench #114 Benjamin Herrenschmidt 2019-10-19 10:31:39 +1100
742b21480e insn: Simplistic implementation of icbi Benjamin Herrenschmidt 2019-10-22 14:56:31 +1100
a0d95e791e insn: Implement isync instruction Benjamin Herrenschmidt 2019-10-22 14:49:35 +1100
6e0ee0b0db icache & dcache: Fix store way variable Benjamin Herrenschmidt 2019-10-17 16:41:19 +1100
587a5e3c45 dcache: Cleanup (mostly cosmetic) Benjamin Herrenschmidt 2019-10-16 15:10:27 +1100
265fbf894b icache/dcache: Make both caches 32 lines, 2 ways Benjamin Herrenschmidt 2019-10-15 16:21:32 +1100
174378b190 dcache: Introduce an extra cycle latency to make timing Benjamin Herrenschmidt 2019-10-10 11:25:16 +1100
b513f0fb48 dcache: Add a dcache Benjamin Herrenschmidt 2019-10-10 00:40:46 +1100
7b3df7cb05 icache: Reduce simulation warnings Benjamin Herrenschmidt 2019-10-10 00:40:11 +1100
a38ae503ff cache_ram: Add write-enables Benjamin Herrenschmidt 2019-10-10 00:38:03 +1100
e598188aca plru: Improve sensitivity list Benjamin Herrenschmidt 2019-10-08 23:26:23 +1100
b963f8a6af

Merge pull request #112 from hughhalf/patch-1 Anton Blanchard 2019-10-21 20:15:37 +1100
96b7f17e52 Minor tweaks to README.md #112 Hugh 2019-10-21 16:51:59 +1100
326dec4b3b

Merge pull request #110 from antonblanchard/misc Anton Blanchard 2019-10-20 10:09:42 +1100
f74e8a4f79 icache_tb: Improve test and include test file #110 Benjamin Herrenschmidt 2019-10-18 16:41:05 +1100
900c131083

Merge pull request #109 from antonblanchard/misc Anton Blanchard 2019-10-17 17:37:49 +1100
e67924f55e isel takes a CR bit, not a CR field #109 Anton Blanchard 2019-10-17 17:16:09 +1100
60b05ee1e5 common: Reformat Benjamin Herrenschmidt 2019-10-16 17:47:08 +1100
bddc9327cc execute1: Remove mux on "write_data" and "rc" outputs Benjamin Herrenschmidt 2019-10-16 12:32:45 +1100
da0bd89c43 crhelpers: Constraint "crnum" integer Benjamin Herrenschmidt 2019-10-16 12:11:16 +1100
4437487ad0 execute1: Reformat Benjamin Herrenschmidt 2019-10-16 12:28:19 +1100
858b1e7930 writeback: Remove a mux leg on data_in Benjamin Herrenschmidt 2019-10-16 12:05:36 +1100
4433118c91

Merge pull request #105 from paulusmack/writeback Anton Blanchard 2019-10-17 07:40:36 +1100
57b200d6cb writeback: Eliminate inferred latch #105 Paul Mackerras 2019-10-16 07:56:15 +1100
bbcc12ac2f

The gammar mistakes were corrected successfully #108 ads123ads 2019-10-15 15:37:45 +0530
640af89e72

Merge pull request #106 from paulusmack/master Anton Blanchard 2019-10-15 21:05:10 +1100
c5ec6aa50a

Update Makefile #107 pragyabansal02 2019-10-15 15:23:50 +0530
a27ed0ec27 wishbone_debug_master: Improve timing #106 Paul Mackerras 2019-10-15 18:16:07 +1100
f49a5a99a5 Remove execute2 stage Paul Mackerras 2019-10-15 16:26:36 +1100
63f5dce820

Merge pull request #104 from paulusmack/master Anton Blanchard 2019-10-15 16:17:12 +1100
9646fe28b0 Do sign-extension instructions in writeback instead of execute1 Paul Mackerras 2019-10-14 14:39:23 +1100
374f4c536d writeback: Do data formatting and condition recording in writeback Paul Mackerras 2019-10-14 12:56:01 +1100
45271acb35

Merge pull request #103 from paulusmack/divider Anton Blanchard 2019-10-15 15:20:34 +1100
86c53aa3f7 Implement neg using OP_ADD #104 Paul Mackerras 2019-10-14 16:02:45 +1100
82c19d4e7a divider: Reduce delay in detecting 32-bit overflow #103 Paul Mackerras 2019-10-15 14:59:15 +1100
6c4edf80ae

Merge pull request #102 from antonblanchard/gpr-hazard-5-c Anton Blanchard 2019-10-15 12:49:06 +1100
813f834012 Add CR hazard detection #102 Anton Blanchard 2019-10-15 11:22:59 +1100
58b348deae

Merge pull request #101 from antonblanchard/gpr-hazard-5-b Anton Blanchard 2019-10-15 11:22:48 +1100
c7025f9f28 divider: Add an output register Paul Mackerras 2019-10-15 10:29:53 +1100
bb65d0b899 Remove issue restrictions on a number of instructions #101 Anton Blanchard 2019-10-14 16:20:07 +1100
bdc26b7527 Add GPR hazard detection Anton Blanchard 2019-10-14 13:27:45 +1100
e4c98dce36

Merge pull request #100 from antonblanchard/gpr-hazard-5-a Anton Blanchard 2019-10-15 09:02:56 +1100
f181bf31e2

Merge pull request #99 from paulusmack/logical Anton Blanchard 2019-10-14 13:14:04 +1100
d5346d0abf Separate issue control into its own unit #100 Anton Blanchard 2019-10-14 12:40:23 +1100
4396eddc31 countzero: Add a testbench #99 Paul Mackerras 2019-10-10 15:09:41 +1100
e527e3a9b7 countzero: Reorganize to have fewer levels of logic and fewer LUTs Paul Mackerras 2019-10-11 16:06:01 +1100
0a0fe03767

Merge pull request #98 from antonblanchard/fix-mod Anton Blanchard 2019-10-13 22:10:18 +1100
10a990bba8 mod* doesn't have an RC form #98 Anton Blanchard 2019-10-13 21:42:27 +1100
56908edea2

Merge pull request #96 from antonblanchard/clk_gen_bypass-fix Anton Blanchard 2019-10-13 15:36:37 +1100
6cdb8ca9f5 Fix clk_gen_bypass #96 Anton Blanchard 2019-10-13 14:41:53 +1100