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caravel-mpw7-20221125
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trace-test
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litedram-update
liteeth-update
fix-sdcard
fpu-init
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caravel-mpw6-20220530
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alt-reset-address
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asic-3
boxarty-20211011
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4 Commits (f812832ad78d422fb5d30b8b6765c236a16b41e2)

Author SHA1 Message Date
Anton Blanchard 34e10cc52c liteeth: Regenerate from upstream litex 
Unfortunately the CSR layout has shifted on upstream litex, so this
is built with the following litex patch backed out:

aad56a047a33 ("integration/soc: Use CSR automatic allocation.")

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 12efb51bcc liteeth: Update yaml config 
csr_data_width is no longer required. Add ntxslots and nrxslots
parameters but set them to the default value.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 458dfe01a6 Add liteeth support to Nexys Video 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Benjamin Herrenschmidt 8366710217 liteeth: Hook up LiteX LiteEth ethernet controller 
Currently only generated for Arty.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago