liteeth: Update yaml config

csr_data_width is no longer required. Add ntxslots and nrxslots
parameters but set them to the default value.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
pull/310/head
Anton Blanchard 3 years ago committed by Anton Blanchard
parent 458dfe01a6
commit 12efb51bcc

@ -8,8 +8,9 @@ vendor: xilinx
clk_freq: 100e6
core: wishbone
endianness: little
ntxslots: 2
nrxslots: 2

soc:
mem_map:
ethmac: 0x00010000
csr_data_width: 32

@ -8,8 +8,9 @@ vendor: xilinx
clk_freq: 125e6
core: wishbone
endianness: little
ntxslots: 2
nrxslots: 2

soc:
mem_map:
ethmac: 0x00010000
csr_data_width: 32

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