The synth target can be used to analyze the core after synthesis
without running P&R. Currently, the only edalize backends that
support synthesis without P&R are vivado and icestorm, and icestorm
needs yosys built with verific support to parse vhdl.
To run synthesis only for a part, run
fusesoc run --target=synth --tool=vivado microwatt --part=<part>
where part is a valid Xilinx part such as xc7a100tcsg324-1
Add a temporary gcc patch to remove hardware divide instructions.
Also add a firmware.hex file built with a gcc with the above patch.
Right now micropython assumes 1MB of BRAM, which limits the FPGAs
we can run on. We should be able to cut it down somewhat.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Dan Horák