Add constraint file for Nexys A7

5 years ago · abca85b034
parent e8ad9bed10
commit abca85b034
1 changed files with 7 additions and 0 deletions
--- a/fpga/nexys_a7.xdc
+++ b/fpga/nexys_a7.xdc
@ -0,0 +1,7 @@
+set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk]
+create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]
+
+set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports reset_n]
+
+set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports uart0_txd]
+set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports uart0_rxd]