Commit Graph

7 Commits (cff4b13a9b8d0036f9441c150bfd8e1d7bc620e3)

Author SHA1 Message Date
Benjamin Herrenschmidt 8e0389b973 ram: Rework main RAM interface
This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Hugh 96b7f17e52 Minor tweaks to README.md
Few tweaks based on a newcomers experience getting an Arty A7-100 up and running

Forgot to add DCO in initial PR, now corrected.

Signed-off-by: Hugh Blemings <hugh@blemings.org>
4 years ago
Cameron Kaiser 07d3c8e4de Add logo to README.md
Signed-off-by: Cameron Kaiser <classilla@floodgap.com>
4 years ago
Anton Blanchard c8328cdf84 Remove gcc software divide patch
We have a divider, thanks to Paul.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Michael Neuling d618171d13 Add pretty gif demo of MicroPython on Microwatt to README.md
Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years ago
Anton Blanchard 77f1588a7f Add some initial FPGA synthesis instructions
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago