Commit Graph

18 Commits (c6ca844c8845eb15aaaf7862f9066cddf9cff2dd)

Author SHA1 Message Date
Anton Blanchard 21f482f967 Reformat testbenches
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
Benjamin Herrenschmidt bf7def5503 soc: Don't require dram wishbones signals to be wired by toplevel
Currently, when not using litedram, the top level still has to hook
up "dummy" wishbones to the main dram and control dram busses coming
out of the SoC and provide ack signals.

Instead, make the SoC generate the acks internally when not using
litedram and use defaults to make the wiring entirely optional.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 1ffc89e58b soc: Add defaults for some input signals
That way the top-level's don't need to assign them

Also remove generics that are set to the default anyways

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 4244b54984 soc: Remove unused RESET_LOW generic
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt cc4dcb3597 spi: Add SPI Flash controller
This adds an SPI flash controller which supports direct
memory-mapped access to the flash along with a manual
mode to send commands.

The direct mode can be set via generic to default to single
wire or quad mode. The controller supports normal, dual and quad
accesses with configurable commands, clock divider, dummy clocks
etc...

The SPI clock can be an even divider of sys_clk starting at 2
(so max 50Mhz with our typical Arty designs).

A flash offset is carried via generics to syscon to tell SW about
which portion of the flash is reserved for the FPGA bitfile. There
is currently no plumbing to make the CPU reset past that address (TBD).

Note: Operating at 50Mhz has proven unreliable without adding some
delay to the sampling of the input data. I'm working in improving
this, in the meantime, I'm leaving the default set at 25 Mhz.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 573b6b4bc4 soc: Rework interconnect
This changes the SoC interconnect such that the main 64-bit wishbone out
of the processor is first split between only 3 slaves (BRAM, DRAM and a
general "IO" bus) instead of all the slaves in the SoC.

The IO bus leg is then latched and down-converted to 32 bits data width,
before going through a second address decoder for the various IO devices.

This significantly reduces routing and timing pressure on the main bus,
allowing to get rid of frequent timing violations when synthetizing on
small'ish FPGAs such as the Artix-7 35T found on the original Arty board.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 025cf5efe8 syscon: Add syscon registers
These provides some info about the SoC (though it's still somewhat
incomplete and needs more work, see comments).

There's also a control register for selecting DRAM vs. BRAM at 0
(and for soft-resetting the SoC but that isn't wired up yet).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 8bb3c8f8b6 soc: Add DRAM address decoding
Still not attached to any board

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 6853d22203 core: Add alternate reset address
An external signal can control whether the core will start
executing at the standard or the alternate reset address.

This will be used when litedram is initialized by microwatt
itself, to route the reset to the built-in init code secondary
block RAM.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Anton Blanchard f5424f8e71 Reduce simulated and default FPGA RAM to 384kB
Micropython has been able to fit into 384kB for ages, so lets reduce our
simulated RAM. This is useful for testing if micropython will run on an
ECP5 85k, which has enough BRAM for 384kB but not enough for 512kB.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Benjamin Herrenschmidt 8e0389b973 ram: Rework main RAM interface
This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 98f0994698 Add core debug module
This module adds some simple core controls:

  reset, stop, start, step

along with icache clear and reading the NIA and core
status bits

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org
4 years ago
Anton Blanchard 89849a6856 Add a simple direct mapped icache
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Benjamin Herrenschmidt 3ac1dbc737 Share soc.vhdl between FPGA and sim
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt c97b080d8c Move wishbone arbiter out of the core
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt 8bfd6e5eae Use simulated UART in core test bench
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Anton Blanchard 1fa0b332ca micropython only requires 512kB of BRAM
Mikey points out that our stack grows down from 512kB and our
heap is below that too, so we can reduce our BRAM requirements,
which allowing some smaller FPGA boards to work. Not sure why
I thought we were using memory between 512kB and 1MB.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago