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caravel-mpw7-20221125
caravel-mpw7-20220822
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trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
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core_debug-init
icache-unused-sig
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divider-init
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fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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2 Commits (c4e3ade4ed1ba7c35fd865ed5b9ce6d4a5c5a886)

Author SHA1 Message Date
Anton Blanchard ab86b58d95 Exit cleanly from testbench on success 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Benjamin Herrenschmidt 004eb074c9 plru: Add a simple PLRU module 
Tested in sim only for now

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago