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3 Commits (b48bf83772516e23605767b5801f45d0cacb1eff)

Author SHA1 Message Date
Anton Blanchard 68495c9b4b ASIC: Switch to ghdl --synth 
Use ghdl --synth to convert to verilog directly instead of going
through Yosys.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 82c8f48f77 ASIC: Fix multiplier power 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 2b47de30c4 Add a script to post process the Microwatt verilog for caravel 
To produce verilog suitable for caravel:

make DOCKER=1 FPGA_TARGET=caravel microwatt_asic.v
./caravel/process-microwatt-verilog.sh

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago