Commit Graph

10 Commits (ae55f5efbd2a57e591a2de31d068a9a974fbe770)

Author SHA1 Message Date
Anton Blanchard b0212b0bf9 Fix ghdlsynth issue in register file
We need to drive sim_dump_done to keep ghdlsynth happy.

Signed-off-by: Anton Blanchard <>
4 years ago
Anton Blanchard 467630573c Dump CTR, LR and CR on sim termination, and update our tests
Right now our test cases fold the SPRs into the GPRs. That makes
debugging fails more difficult than it needs to be, so print
out the CTR, LR and CR.

We still need to print the XER, but that is in two spots in microwatt
and will take some more work.

This also adds many instructions to the tests that we have added
lately including overflow instructions, CR logicals and mt/mfxer.

Signed-off-by: Anton Blanchard <>
4 years ago
Benjamin Herrenschmidt e4f475e17f sprs: Store common SPRs in register file
This stores the most common SPRs in the register file.

This includes CTR and LR and a not yet final list of others.

The register file is set to 64 entries for now. Specific types
are defined that can represent a GPR index (gpr_index_t) or
a GPR/SPR index (gspr_index_t) along with conversion functions
between the two.

On order to deal with some forms of branch updating both LR and
CTR, we introduced a delayed update of LR after a branch link.

Note: We currently stall the pipeline on such a delayed branch,
but we could avoid stalling fetch in that specific case as we
know we have a branch delay. We could also limit that to the
specific case where we need to update both CTR and LR.

This allows us to make bcreg, mtspr and mfspr pipelined. decode1
will automatically force the single issue flag on mfspr/mtspr to
a "slow" SPR.

[ - fix direction of decode2.stall_in]

Signed-off-by: Benjamin Herrenschmidt <>
Signed-off-by: Paul Mackerras <>
4 years ago
Tristan Gingold 0169d48ee6 Fix register file size (there are 32 gprs). 5 years ago
Benjamin Herrenschmidt ec1868f7d2 register_file: Move GPRs into distributed RAM
The register file is currently implemented as a whole pile of individual
1-bit registers instead of LUT memory which is a huge waste of FPGA

This is caused by the output signal exposing the register file to the
outside world for simulation debug.

This removes that output, and moves the dumping of the register file
to the register file module itself. This saves about 8% of fpga on
the little Arty A7-35T.

Signed-off-by: Benjamin Herrenschmidt <>
5 years ago
Anton Blanchard 4d9b2a1165 Reformat register file
Signed-off-by: Anton Blanchard <>
5 years ago
Anton Blanchard 79a14c8e37 Add forwarding in the register file
We need this for the upcoming pipelining patches.

Signed-off-by: Anton Blanchard <>
5 years ago
Anton Blanchard 31a6fb6ef5 More second write port removal
I missed the register file updates for the second write port

Signed-off-by: Anton Blanchard <>
5 years ago
Anton Blanchard 04eb9583e6 Clean up register read debug output
Right now we continually print all 3 possible GPRs an instruction
may be using. Add signals so we only print GPRs when they are
actually read. This should hopefully optimise away when synthesized.

Signed-off-by: Anton Blanchard <>
5 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt
Signed-off-by: Anton Blanchard <>
5 years ago