58 Commits (a740c4b7af6b25301fbe036ab92417d57fb4277d)

Author	SHA1	Message	Date
Anton Blanchard	0a0ad9b384	Rebuild hello world assuming a 50MHz clock ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	6 years ago
Olof Kindgren	12327034d6	Add and use plle2 primitive for nexys boards	6 years ago
Anton Blanchard	8bc3e8ea0a	Add a simple hello_world example that also echos input ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	6 years ago
Olof Kindgren	abca85b034	Add constraint file for Nexys A7	6 years ago
Olof Kindgren	e8ad9bed10	Expose ram init file and memory size through toplevel	6 years ago
Olof Kindgren	b5bccc4c13	Add dummy clock generator	6 years ago
Anton Blanchard	37fe8b954c	Add a few more FPGA related files ... Add a temporary gcc patch to remove hardware divide instructions. Also add a firmware.hex file built with a gcc with the above patch. Right now micropython assumes 1MB of BRAM, which limits the FPGAs we can run on. We should be able to cut it down somewhat. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	6 years ago
Anton Blanchard	5a29cb4699	Initial import of microwatt ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	6 years ago