cores
/
microwatt
mirror of https://github.com/antonblanchard/microwatt
3
1
Fork 1
Code Issues Projects Releases Wiki Activity
551 Commits
39 Branches
0 Tags
68 MiB
master
caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '8c028f26f1'
${ noResults }
Commit Graph

2 Commits (8c028f26f1e7092ef34d1c7806328a4e2fa5fba7)

Author SHA1 Message Date
Anton Blanchard f96d179f66 Some yosys fixes 
This gets the yosys build further along, but I'm now chasing what looks
like a yosys bug.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Benjamin Herrenschmidt 3ac815823c fpga: Hookup Arty to litedram 
The old toplevel.vhdl becomes top-generic.vhdl, which is to be used
by platforms that do not have a litedram option.

Arty has its own top-arty.vhdl which supports litedram and is now
hooked up

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago