Some yosys fixes

This gets the yosys build further along, but I'm now chasing what looks
like a yosys bug.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

Makefile.synth

@@ -52,8 +52,8 @@ VHDL_FILES += ppc_fx_insns.vhdl execute1.vhdl decode1.vhdl cr_file.vhdl
 VHDL_FILES += writeback.vhdl loadstore1.vhdl icache.vhdl cr_hazard.vhdl
 VHDL_FILES += gpr_hazard.vhdl control.vhdl decode2.vhdl core.vhdl
 VHDL_FILES += fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd dmi_dtm_dummy.vhdl
-VHDL_FILES += fpga/main_bram.vhdl wishbone_bram_wrapper.vhdl soc.vhdl
-VHDL_FILES += fpga/toplevel.vhdl
+VHDL_FILES += fpga/main_bram.vhdl wishbone_bram_wrapper.vhdl syscon.vhdl
+VHDL_FILES += xics.vhdl soc.vhdl fpga/top-generic.vhdl
 
 all: microwatt.bit
 

fpga/top-generic.vhdl

@@ -1,6 +1,9 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
+library work;
+use work.wishbone_types.all;
+
 entity toplevel is
     generic (
 	MEMORY_SIZE   : positive := (384*1024);
@@ -68,13 +71,16 @@ begin
 	    RAM_INIT_FILE => RAM_INIT_FILE,
 	    RESET_LOW     => RESET_LOW,
 	    SIM           => false,
+	    CLK_FREQ      => CLK_FREQUENCY,
 	    DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE
 	    )
 	port map (
 	    system_clk        => system_clk,
 	    rst               => soc_rst,
 	    uart0_txd         => uart0_txd,
-	    uart0_rxd         => uart0_rxd
+	    uart0_rxd         => uart0_rxd,
+	    wb_dram_out       => wb_dram_out,
+	    alt_reset         => '0'
 	    );
 
     -- Dummy DRAM