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7 Commits (7aaed5abd512897fc47eef8d0624cc3d4de6cb93)

Author SHA1 Message Date
Benjamin Herrenschmidt 48e6e719d3 Multiply needs to be 16 stages to fix all timing issues 
This seems dependent on the FPGA type/size, so we should probably
make it a toplevel generic, but for now this helps on the
Arty A7-35

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Anton Blanchard 8dd97fbe7f Reformat multiply code 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 99dd4de54e Don't use VHDL 2008 condition operator in multiply 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 68533c4cfb Reduce multiply to 2 cycles 
We want all non load/store ops to take 2 cycles to make
tracking write back easier.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard a22afbdb5b Quieten multiply warning 
We no longer gate multiply with the valid signal, so it's complaining
a lot. Comment out the warning.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 18b9b39a2c Simplify multiply 
No need to gate everything with the valid bit.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago