Don't use VHDL 2008 condition operator in multiply

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
pull/63/head
Anton Blanchard 5 years ago committed by Anton Blanchard
parent 550b2b8608
commit 99dd4de54e

@ -85,7 +85,7 @@ begin
m_out.write_reg_data <= d2;
m_out.write_reg_nr <= v.multiply_pipeline(PIPELINE_DEPTH-1).write_reg;

if v.multiply_pipeline(PIPELINE_DEPTH-1).valid then
if v.multiply_pipeline(PIPELINE_DEPTH-1).valid = '1' then
m_out.valid <= '1';
m_out.write_reg_enable <= '1';


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