These instructions are similar to those at
https://ozlabs.org/~joel/microwatt/README
except they describe how to build the artifacts from scratch instead of
downloading them.
Signed-off-by: Joel Stanley <joel@jms.id.au>
The SoC defaults to using the uart16550 so provide instructions on how
to fetch that library when seetting up fusesoc.
Also remove the text about a working directory; fusesoc doesn't need
one.
Signed-off-by: Joel Stanley <joel@jms.id.au>
We've had these for a while now:
- D/I cache
- GPR bypassing
- Supervisor state (and can boot linux)
We still need Vector/VMX/VSX (and probably some other things)
Signed-off-by: Michael Neuling <mikey@neuling.org>
Update documentation to reference fusesoc init for Xilinx boards, for
those like me who have never used fusesoc before. Add a reference to the
board files for Digilent boards and comment on perhaps installing them
for other boards as appropriate.
Signed-off-by: Antony Vennard <antony@vennard.ch>
A number of people have tripped up on GHDL backend issues. We
require either the LLVM or gcc backend, because the mcode backend
can't link against libraries which we use for simulated memory
and UART. Make that clearer, and point people at the Docker images
if they are having issues building ghdl.
Also point at the prebuilt micropython image.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Few tweaks based on a newcomers experience getting an Arty A7-100 up and running
Forgot to add DCO in initial PR, now corrected.
Signed-off-by: Hugh Blemings <hugh@blemings.org>
Joel Stanley
Michael Neuling
Paul Mackerras