Commit Graph

849 Commits (5f8279a14ab2921df91babd684f6a4991c59ac29)
 

Author SHA1 Message Date
Paul Mackerras 5f8279a14a
Merge pull request #263 from antonblanchard/reset-pid
Initialize PID register
3 years ago
Paul Mackerras 45b7312e89
Merge pull request #262 from antonblanchard/reset-tb-decr
Reset TB and DECR
3 years ago
Paul Mackerras 00446a9169
Merge pull request #259 from antonblanchard/dmi-reset
Reset JTAG/DMI
3 years ago
Anton Blanchard 3f1e2b3a4f
Merge pull request #265 from antonblanchard/another-spi-rxtx-reset-issu
Fix another reset issue in spi_rxtx
3 years ago
Anton Blanchard 75be7803b2
Merge pull request #264 from antonblanchard/reset-spi-txrx
Reset cmd_ready_o in spi_txrx
3 years ago
Anton Blanchard 740f013284 Initialize PID register
If the PID register is read before it is written we'll consume
X state data.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
Anton Blanchard a0eb4eec17 Fix another reset issue in spi_rxtx
counter was X state after reset, initialize it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
Anton Blanchard bf9a446e3f Reset cmd_ready_o in spi_txrx
Initialize bit_count so that cmd_ready_o isn't X state immediately
after reset.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
Anton Blanchard e1bac4d6e7 Reset TB and DECR
We don't care what the values of TB and DECR are after reset, but we
don't want the X state to propagate to other parts of the chip.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
Anton Blanchard 39c826aa46
Merge pull request #261 from antonblanchard/wishbone_layout
Make wishbone_master_out and wb_io_master_out match
3 years ago
Anton Blanchard ebe696affc
Merge pull request #260 from paulusmack/misc
soc: Drive uart1_irq to 0 when we don't have UART1
3 years ago
Anton Blanchard c6dfc19d89 Make wishbone_master_out and wb_io_master_out match
This makes it easier to parse the records in verilog because they
are getting flattened into an array of bits by ghdl/yosys.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
Paul Mackerras e41cb01bca fetch1: Fix debug stop
The ability to stop the core using the debug interface has been broken
since commit bb4332b7e6b5 ("Remove fetch2 pipeline stage"), which
removed a statement that cleared the valid bit on instructions when
their stop_mark was 1.

Fix this by clearing r.req coming out of fetch1 when r.stop_mark = 1.
This has the effect of making i_out.valid be 0 from the icache.  We
also fix a bug in icache.vhdl where it was not honouring i_in.req when
use_previous = 1.

It turns out that the logic in fetch1.vhdl to handle stopping and
restarting was not correct, with the effect that stopping the core
would leave NIA pointing to the last instruction executed, not the
next instruction to be executed.  In fact the state machine is
unnecessary and the whole thing can be simplified enormously - we
need to increment NIA whenever stop_in = 0 in the previous cycle.

Fixes: bb4332b7e6b5 ("Remove fetch2 pipeline stage")
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years ago
Paul Mackerras 97586e7e99 soc: Drive uart1_irq to 0 when we don't have UART1
The tools complain about uart1_irq not being driven and not having a
default when HAS_UART1 is false.  This sets it to 0 in that case.

Fixes: 7575b1e0c2 ("uart: Import and hook up opencore 16550 compatible UART")
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years ago
Anton Blanchard 5eb351b4be Reset JTAG/DMI
request is never initialized and we leak X state control signals to other
parts of the core (eg dmi_wr). Add a reset.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
Michael Neuling d96ee21c39
Merge pull request #256 from antonblanchard/flash-reset
Fix a few reset issues in flash controller
3 years ago
Paul Mackerras f4831507b3
Merge pull request #257 from antonblanchard/nofpu-fix
Fully initialize FPU buses when FPU is disabled
3 years ago
Anton Blanchard c870040a20 Fix an issue in flash controller when BOOT_CLOCKS is false
If BOOT_CLOCKS is false we currently get stuck in the flash
state machine. This patch from Ben fixes it.

Also fix an x state issue I see in icarus verilog where we need
to reset auto_state.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
Anton Blanchard 659be2780f Fully initialize FPU buses when FPU is disabled
Some of the bits in the FPU buses end up as z state. Yosys
flags them, so we may as well clean it up.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 7c8bc85e44 Fix a few reset issues in flash controller
Our flash controller fails when simulating with iverilog. Looking
closer, both wb_stash and auto_last_addr are X state, and things
fall apart after they get used.

Initialise them both fixes the iverilog issue.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 081dc64d39
Merge pull request #255 from antonblanchard/log-length
Add LOG_LENGTH to top-generic.vhdl
4 years ago
Anton Blanchard 86bdfe6fd4
Merge pull request #254 from antonblanchard/fix-verilator
Add verilator FPGA target
4 years ago
Anton Blanchard 80cf489e96 Add LOG_LENGTH to top-generic.vhdl
The other top level files allow LOG_LENGTH to be configured.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard df8e1ca2a7 Add verilator FPGA target
Our Makefiles need some work, but for now create an FPGA target:

make FPGA_TARGET=verilator microwatt-verilator

ghdl and yosys can use containers using PODMAN=1 or DOCKER=1
options.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 62d5b16c66
Merge pull request #253 from antonblanchard/fix-verilator
Fix verilator build
4 years ago
Anton Blanchard 4bc5169f78 Fix verilator build
yosys and verilator did not like us passing in the verilog and
exporting it again. Pass the source directly to verilator instead.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Michael Neuling 77c03e5d42
Merge pull request #252 from antonblanchard/hello-world-in-8k
Reduce hello_world footprint to fit in 8kB
4 years ago
Anton Blanchard 605010e33d Fix ghdl warning due to variable shadowing in icache
Fix a couple of ghdl warnings:

icache.vhdl:387:21⚠️ declaration of "i" hides constant "i" [-Whide]
icache.vhdl:400:17⚠️ declaration of "i" hides constant "i" [-Whide]

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard bc4e6b7efe Reduce hello_world footprint to fit in 8kB
When building with yosys we assume hello_world fits in 8kB. There's
enough free space that we can adjust the linker script to make it fit.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Michael Neuling 16da9b5ba7
Merge pull request #249 from paulusmack/master
Sundry bug fixes, plus implement mtmsr
4 years ago
Michael Neuling b60026e7c1
Merge pull request #250 from umarcor/containers
makefile: update synthesis containers
4 years ago
Michael Neuling d839037f0b
Merge pull request #251 from umarcor/ci/containers
ci: use job.container
4 years ago
umarcor 93b2987b19 ci: use job.container
Signed-off-by: umarcor <unai.martinezcorral@ehu.eus>
4 years ago
umarcor de808d7a6a makefile: update synthesis containers
Signed-off-by: umarcor <unai.martinezcorral@ehu.eus>
4 years ago
umarcor d05737833e makefile: whitespace cleanup
Signed-off-by: umarcor <unai.martinezcorral@ehu.eus>
4 years ago
Paul Mackerras 29fabeb12e tests/misc: Add a test for correct CTR and LR updating by branches
This adds a test with a bdnzl followed immediately by a bdnz, to check
that CTR and LR both get evaluated and written back correctly in this
situation.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras e49192cb5b execute1: Fix forwarding of result when doing delayed LR update
Random execution testcases showed that a bdnzl which doesn't branch,
followed immediately by a bdnz, uses the wrong value for CTR for the
bdnz.  Decode2 detects the read-after-write hazard on CTR and tells
execute1 to use the bypass path.  However, the bdnzl takes two cycles
because it has to write back both CTR and LR, meaning that by the time
the bdnz starts to execute, r.e.write_data no longer contains the CTR
value, but instead contains zero.

To fix this, we make execute1 maintain the written-back value of CTR
in r.e.write_data across the cycle where LR is written back (this is
possible because the LR writeback uses the exc_write_data path).

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 27ac74a341 execute1: Fix writing LR for bdnzl/bdzl instructions
Branch instructions which do a redirect and write both CTR and LR were
not doing the write to LR due to a logic error.  This fixes it.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 1037c6aa2e core: Implement mtmsr instruction
This is like mtmsrd except it only alters the lower 32 bits of the MSR.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 144433218f tests/trace: Test trace interrupt vs. FP unavailable interrupt
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras b0f7237b7f execute1: Fix bug in trace interrupt vs. ITLB miss
If an instruction fetch results in an instruction TLB miss, an
OP_FETCH_FAILED instruction is sent down the pipe.  If the MSR[TE]
field is set for instruction tracing, the core currently considers
that executing the OP_FETCH_FAILED counts as having executed one
instruction and so generates a trace interrupt on the next valid
instruction, meaning that the trace interrupt happens before the
desired instruction rather than after it.

Fix this by not tracing OP_FETCH_FAILED instructions.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Michael Neuling e40e752b9a
Merge pull request #245 from paulusmack/fpu
Add a simple FPU
4 years ago
Michael Neuling 168d30c07a
Merge pull request #244 from paulusmack/master
Implement trace interrupts plus decode improvements
4 years ago
Paul Mackerras 73f819301b FPU: Do masking after adder rather than on A input
The masking enabled by opsel_amask is only used when rounding, to trim
the rounded result to the required precision.  We now do the masking
after the adder rather than before (on the A input).  This gives the
same result and helps timing.  The path from r.shift through the mask
generator and adder to v.r was showing up as a critical path.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras e1ca023bad FPU: Decide on mask length a cycle earlier
This moves longmask into the reg_type record, meaning that it now
needs to be decided a cycle earlier, in order to help timing.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras fb5115c944 FPU: Decide on A input selection a cycle earlier
This moves opsel_a into the reg_type record, meaning that the A
multiplexer input now needs to be decided a cycle earlier.  This helps
timing by eliminating the combinatorial path from r.state and other
things to opsel_a and thence to in_a and result.

This means that some things now take an extra cycle, in particular
some of the exception cases such as when one or both operands are
NaNs.  The NaN handling has been moved out to its own state, which
simplifies the logic for exception cases in other places.  Additions
or subtractions where FRB's exponent is smaller than FRA's will
also take an extra cycle.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras b0b3c0dc70 FPU: Add comments specifying the expectation of r.shift for each state
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras dc1544db69 FPU: Implement floating multiply-add instructions
This implements fmadd, fmsub, fnmadd, fnmsub and their
single-precision counterparts.  The single-precision versions operate
the same as the double-precision versions until the final rounding and
overflow/underflow steps.

This adds an S register to store the low bits of the product.  S
shifts into R on left shifts, and can be negated, but doesn't do any
other arithmetic.

This adds a test for the double-precision versions of these
instructions.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras c083b9507d FPU: Implement ftdiv and ftsqrt
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras c350bc1f25 FPU: Implement fsqrt[s] and add a test for fsqrt
This implements the floating square-root calculation using a table
lookup of the inverse square root approximation, followed by three
iterations of Goldschmidt's algorithm, which gives estimates of both
sqrt(FRB) and 1/sqrt(FRB).  Then the residual is calculated as
FRB - R * R and that is multiplied by the 1/sqrt(FRB) estimate to get
an adjustment to R.  The residual and the adjustment can be negative,
and since we have an unsigned multiplier, the upper bits can be wrong.
In practice the adjustment fits into an 8-bit signed value, and the
bottom 8 bits of the adjustment product are correct, so we sign-extend
them, divide by 4 (because R is in 10.54 format) and add them to R.

Finally the residual is calculated again and compared to 2*R+1 to see
if a final increment is needed.  Then the result is rounded and
written back.

This implements fsqrts as fsqrt, but with rounding to single precision
and underflow/overflow calculation using the single-precision exponent
range.  This could be optimized later.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago