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caravel-mpw7-20221125
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trace-test
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litedram-update
liteeth-update
fix-sdcard
fpu-init
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fpu-typo
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caravel-mpw6-20220530
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alt-reset-address
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boxarty-20211011
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remove-potato-uart
cache-tlb-parameters-2
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2 Commits (5860c2d1b6ed52a5d5c85586c591475513c9528a)

Author SHA1 Message Date
Anton Blanchard 471c7e2197 Consolidate VHPI code 
We had many copies of the VHPI marshalling/unmarshalling code.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Benjamin Herrenschmidt 8e0389b973 ram: Rework main RAM interface 
This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago