We might want a non power of 2 amount of RAM in order to fit into an
FPGA, so create log2ceil and use it when calculating the number of
Signed-off-by: Anton Blanchard <firstname.lastname@example.org>
This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.
Signed-off-by: Benjamin Herrenschmidt <email@example.com>