2f3ca35a6e
Merge pull request #42 from antonblanchard/fetch-rework-v2
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Fetch rework
5 years ago
4528ef2b43
Reformat core.vhdl
5 years ago
a2df2a10a2
Remove sim console
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We can force all existing code to use the UART console
by passing 0 in bit zero of the sim config register.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
68533c4cfb
Reduce multiply to 2 cycles
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We want all non load/store ops to take 2 cycles to make
tracking write back easier.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
9fe8d211eb
Register outputs on writeback
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
c7aa683ba8
Register outputs on execute2
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
819f820090
Register outputs on loadstore1
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
a8f8c54b77
Move debug execute output into decode2
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This covers all units, and we avoid double printing.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
92a7152370
Rework pipeline, add stall and flush signals
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This adds stall and flush signals to the pipeline.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
3b32abcb5d
Merge pull request #40 from antonblanchard/makefile-dependencies
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Update Makefile dependencies
5 years ago
b6b2c78163
Update Makefile dependencies
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
d3acb5cce9
Switch soc to use std_ulogic
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3ac1dbc737
Share soc.vhdl between FPGA and sim
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
d21ef5836d
Pass wishbone record to bram memory module
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(And rename it to mw_soc_memory).
This makes soc.vhdl simpler and provides the same interface as
the simulated memory, which will help when sharing soc.vhdl
with sim later
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
1d66e1f981
Rework wishbone slave address decoding
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Don't make it synchronous, no latches
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
c97b080d8c
Move wishbone arbiter out of the core
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
310a56c076
Re-indent and reformat soc.vhdl
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
a69a93b466
Split FPGA toplevel from soc
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This will be useful when we start needing different toplevels for
different boards.
We keep the reset and clock generators in the toplevel as they will
eventually be taken over by litedram when we integrate it, and they
are more likely to change on different system types.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
5ee86e7621
Merge pull request #39 from antonblanchard/no-x-state
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Don't send out X state from the memory behavioural
5 years ago
dce2e06f4c
Don't send out X state from the memory behavioural
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Just send out all 1s.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
c3a5782bf4
Merge pull request #36 from mikey/gitignore
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Add new files to git ignore
5 years ago
419b95a447
Merge pull request #38 from antonblanchard/multiply-warn
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Quieten multiply warning
5 years ago
a22afbdb5b
Quieten multiply warning
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We no longer gate multiply with the valid signal, so it's complaining
a lot. Comment out the warning.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Michael Neuling
5ae92a721f
Add new files to git ignore
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Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years ago
d79c994158
Merge pull request #35 from antonblanchard/multiply-opt
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Simplify multiply
5 years ago
18b9b39a2c
Simplify multiply
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No need to gate everything with the valid bit.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
47f39440f2
Merge pull request #34 from antonblanchard/decode-table
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Decode table
5 years ago
9687034d78
Add a decode bit to mark an instruction as single through the pipeline
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This is used by the pipelining patches. Mark everyone as single through
the pipeline to start.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
b0ade2857f
decode1 array fix header
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
a9065796ad
Merge pull request #33 from antonblanchard/cr-fix
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Fix CR forwarding
5 years ago
e0dfb3dce1
Merge pull request #32 from antonblanchard/register-file-forwarding
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Add forwarding in the register file
5 years ago
8bfd6e5eae
Use simulated UART in core test bench
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
1b9c6f4647
Make sim poll non-blocking
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
48b689b665
Add simulated UART design
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
9cbdecb561
Fix CR forwarding
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We weren't actually forwarding writes in the same cycle. Not a
problem right now, but noticed when testing the pipelining series.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
79a14c8e37
Add forwarding in the register file
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We need this for the upcoming pipelining patches.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
2241b71674
Merge pull request #31 from antonblanchard/no-second-write-port-2
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More second write port removal
5 years ago
045a00c5d7
Merge pull request #30 from antonblanchard/writeback-assert
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Add some assertions to writeback
5 years ago
31a6fb6ef5
More second write port removal
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I missed the register file updates for the second write port
removal.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
fa04936c92
Add some assertions to writeback
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We want to make sure we never complete more than one
instruction per cycle, or write back more than one GPR
or CR per cycle.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
4c872619b3
Merge pull request #29 from antonblanchard/no-second-write-port
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Remove second write port
5 years ago
f384f504a1
Merge pull request #28 from antonblanchard/loadstore-cleanup
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Remove some more loadstore debug
5 years ago
fb4cad6eaf
Remove second write port
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We only need two write ports for load with update instructions.
Having two write ports just for this instruction is expensive.
For now we will force them to be the only instruction in the
pipeline, and take two cycles of writeback.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
aee5fded44
Remove some more loadstore debug
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
ff9070d727
Merge pull request #27 from antonblanchard/fix-cr
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Fix issues with CR rework
5 years ago
0254e40685
Fix issues with CR rework
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It simulated fine, but didn't synthesize. Fix some obvious issues
to get us going again.
Fixes: 9fbaea6f08
5 years ago
b8d93728d7
Merge pull request #26 from antonblanchard/silence-loadstore-debug
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Silence some loadstore related debug
5 years ago
a1ab1d3e56
Merge pull request #25 from antonblanchard/register_file_printing
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Clean up register read debug output
5 years ago
a5d31bb554
Merge pull request #24 from antonblanchard/cr_file_cleanup
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Rework CR file and add forwarding
5 years ago
5d82af5204
Silence some loadstore related debug
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard
Michael Neuling