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microwatt
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caravel-mpw7-20221125
caravel-mpw7-20220822
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trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
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dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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Commit Graph

7 Commits (12327034d6308c8ddc2397387e5cfa610e422b55)

Author SHA1 Message Date
Olof Kindgren 12327034d6 Add and use plle2 primitive for nexys boards 6 years ago
Anton Blanchard 8bc3e8ea0a Add a simple hello_world example that also echos input 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Olof Kindgren abca85b034 Add constraint file for Nexys A7 6 years ago
Olof Kindgren e8ad9bed10 Expose ram init file and memory size through toplevel 6 years ago
Olof Kindgren b5bccc4c13 Add dummy clock generator 6 years ago
Anton Blanchard 37fe8b954c Add a few more FPGA related files 
Add a temporary gcc patch to remove hardware divide instructions.

Also add a firmware.hex file built with a gcc with the above patch.

Right now micropython assumes 1MB of BRAM, which limits the FPGAs
we can run on. We should be able to cut it down somewhat.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago