Commit Graph

5 Commits (caravel-mpw7-20221125)

Author SHA1 Message Date
Anton Blanchard 9366d23f1f ASIC: No need to add includes any more
The simulation scripts include the necessary files.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
1 year ago
Anton Blanchard 64997811a8 Fix power plumbing in execute unit 1 year ago
Anton Blanchard 68495c9b4b ASIC: Switch to ghdl --synth
Use ghdl --synth to convert to verilog directly instead of going
through Yosys.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard 82c8f48f77 ASIC: Fix multiplier power
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago
Anton Blanchard 2b47de30c4 Add a script to post process the Microwatt verilog for caravel
To produce verilog suitable for caravel:

make DOCKER=1 FPGA_TARGET=caravel microwatt_asic.v
./caravel/process-microwatt-verilog.sh

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago