Merge pull request #399 from ozbenh/misc

Fix PLRU
pull/402/head
Michael Neuling 2 years ago committed by GitHub
commit cf6d57b803
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GPG Key ID: 4AEE18F83AFDEB23

@ -19,8 +19,12 @@ entity plru is
end entity plru; end entity plru;


architecture rtl of plru is architecture rtl of plru is
-- Each level of the tree (from leaf to root) has half the number of nodes
-- of the previous level. So for a 2^N bits LRU, we have a level of N/2 bits
-- one of N/4 bits etc.. down to 1. This gives us 2^N-1 nodes. Ie, 2 bits
-- LRU has 3 nodes (2 + 1), 4 bits LRU has 15 nodes (8 + 4 + 2 + 1) etc...
constant count : positive := 2 ** BITS - 1; constant count : positive := 2 ** BITS - 1;
subtype node_t is integer range 0 to count; subtype node_t is integer range 0 to count - 1;
type tree_t is array(node_t) of std_ulogic; type tree_t is array(node_t) of std_ulogic;


signal tree: tree_t; signal tree: tree_t;
@ -31,14 +35,16 @@ begin
-- in term of FPGA resource usage... -- in term of FPGA resource usage...
get_lru: process(tree) get_lru: process(tree)
variable node : node_t; variable node : node_t;
variable abit : std_ulogic;
begin begin
node := 0; node := 0;
for i in 0 to BITS-1 loop for i in 0 to BITS-1 loop
-- report "GET: i:" & integer'image(i) & " node:" & integer'image(node) & " val:" & std_ulogic'image(tree(node)); -- report "GET: i:" & integer'image(i) & " node:" & integer'image(node) & " val:" & std_ulogic'image(tree(node));
lru(BITS-1-i) <= tree(node); abit := tree(node);
lru(BITS-1-i) <= abit;
if i /= BITS-1 then if i /= BITS-1 then
node := node * 2; node := node * 2;
if tree(node) = '1' then if abit = '1' then
node := node + 2; node := node + 2;
else else
node := node + 1; node := node + 1;
@ -71,5 +77,10 @@ begin
end loop; end loop;
end if; end if;
end if; end if;
-- if falling_edge(clk) then
-- if acc_en = '1' then
-- report "UPD: tree:" & to_string(tree);
-- end if;
-- end if;
end process; end process;
end; end;

@ -56,58 +56,74 @@ begin
begin begin
test_runner_setup(runner, runner_cfg); test_runner_setup(runner, runner_cfg);


wait for 4*clk_period; wait for 8*clk_period;

info("reset state:" & to_hstring(lru));
check_equal(lru, 0, result("LRU"));


info("accessing 1:"); info("accessing 1:");
acc <= "001"; acc <= "001";
acc_en <= '1'; acc_en <= '1';
wait for clk_period; wait for clk_period;
info("lru:" & to_hstring(lru)); info("lru:" & to_hstring(lru));
check_equal(lru, 4, result("LRU"));


info("accessing 2:"); info("accessing 2:");
acc <= "010"; acc <= "010";
wait for clk_period; wait for clk_period;
info("lru:" & to_hstring(lru)); info("lru:" & to_hstring(lru));
check_equal(lru, 4, result("LRU"));


info("accessing 7:"); info("accessing 7:");
acc <= "111"; acc <= "111";
wait for clk_period; wait for clk_period;
info("lru:" & to_hstring(lru)); info("lru:" & to_hstring(lru));
check_equal(lru, 0, result("LRU"));


info("accessing 4:"); info("accessing 4:");
acc <= "100"; acc <= "100";
wait for clk_period; wait for clk_period;
info("lru:" & to_hstring(lru)); info("lru:" & to_hstring(lru));
check_equal(lru, 0, result("LRU"));


info("accessing 3:"); info("accessing 3:");
acc <= "011"; acc <= "011";
wait for clk_period; wait for clk_period;
info("lru:" & to_hstring(lru)); info("lru:" & to_hstring(lru));
check_equal(lru, 6, result("LRU"));


info("accessing 5:"); info("accessing 5:");
acc <= "101"; acc <= "101";
wait for clk_period; wait for clk_period;
info("lru:" & to_hstring(lru)); info("lru:" & to_hstring(lru));
check_equal(lru, 0, result("LRU"));


info("accessing 3:"); info("accessing 3:");
acc <= "011"; acc <= "011";
wait for clk_period; wait for clk_period;
info("lru:" & to_hstring(lru)); info("lru:" & to_hstring(lru));
check_equal(lru, 6, result("LRU"));


info("accessing 5:"); info("accessing 5:");
acc <= "101"; acc <= "101";
wait for clk_period; wait for clk_period;
info("lru:" & to_hstring(lru)); info("lru:" & to_hstring(lru));
check_equal(lru, 0, result("LRU"));


info("accessing 6:"); info("accessing 6:");
acc <= "110"; acc <= "110";
wait for clk_period; wait for clk_period;
info("lru:" & to_hstring(lru)); info("lru:" & to_hstring(lru));
check_equal(lru, 0, result("LRU"));


info("accessing 0:"); info("accessing 0:");
acc <= "000"; acc <= "000";
wait for clk_period; wait for clk_period;
info("lru:" & to_hstring(lru)); info("lru:" & to_hstring(lru));
check_equal(lru, 4, result("LRU"));

wait for clk_period;
wait for clk_period;
test_runner_cleanup(runner); test_runner_cleanup(runner);
end process; end process;

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