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Merge pull request #147 from antonblanchard/diamond-1

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Some Diamond fixes
pull/152/head
Anton Blanchard 5 years ago committed by GitHub
parent 39596dc70a 098f10136d
commit a2bf039a70
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 22 additions and 19 deletions
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29
decode2.vhdl
Unescape Escape View File

@ -79,32 +79,33 @@ architecture behaviour of decode2 is
function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0); function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
reg_data : std_ulogic_vector(63 downto 0); reg_data : std_ulogic_vector(63 downto 0);
ispr : gspr_index_t) return decode_input_reg_t is ispr : gspr_index_t) return decode_input_reg_t is
variable ret : decode_input_reg_t;
begin begin
case t is case t is
when RB => when RB =>
assert is_fast_spr(ispr) = '0' report "Decode B says GPR but ISPR says SPR:" & assert is_fast_spr(ispr) = '0' report "Decode B says GPR but ISPR says SPR:" &
to_hstring(ispr) severity failure; to_hstring(ispr) severity failure;
return ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data); ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
when CONST_UI => when CONST_UI =>
return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64))); ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
when CONST_SI => when CONST_SI =>
return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64))); ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
when CONST_SI_HI => when CONST_SI_HI =>
return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64))); ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
when CONST_UI_HI => when CONST_UI_HI =>
return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64))); ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
when CONST_LI => when CONST_LI =>
return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64))); ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
when CONST_BD => when CONST_BD =>
return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64))); ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
when CONST_DS => when CONST_DS =>
return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64))); ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
when CONST_M1 => when CONST_M1 =>
return ('0', (others => '0'), x"FFFFFFFFFFFFFFFF"); ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
when CONST_SH => when CONST_SH =>
return ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11)); ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
when CONST_SH32 => when CONST_SH32 =>
return ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11)); ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
when SPR => when SPR =>
-- ISPR must be either a valid fast SPR number or all 0 for a slow SPR. -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
-- If it's all 0, we don't treat it as a dependency as slow SPRs -- If it's all 0, we don't treat it as a dependency as slow SPRs
@ -112,10 +113,12 @@ architecture behaviour of decode2 is
assert is_fast_spr(ispr) = '1' or ispr = "000000" assert is_fast_spr(ispr) = '1' or ispr = "000000"
report "Decode B says SPR but ISPR is invalid:" & report "Decode B says SPR but ISPR is invalid:" &
to_hstring(ispr) severity failure; to_hstring(ispr) severity failure;
return (is_fast_spr(ispr), ispr, reg_data); ret := (is_fast_spr(ispr), ispr, reg_data);
when NONE => when NONE =>
return ('0', (others => '0'), (others => '0')); ret := ('0', (others => '0'), (others => '0'));
end case; end case;

return ret;
end; end;


function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0); function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);

12
writeback.vhdl
Unescape Escape View File

@ -64,16 +64,16 @@ begin
variable zero : std_ulogic; variable zero : std_ulogic;
variable sign : std_ulogic; variable sign : std_ulogic;
begin begin
x := "" & e_in.valid; x(0) := e_in.valid;
y := "" & l_in.valid; y(0) := l_in.valid;
assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure; assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure;


x := "" & e_in.write_enable; x(0) := e_in.write_enable;
y := "" & l_in.write_enable; y(0) := l_in.write_enable;
assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure; assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure;


w := "" & e_in.write_cr_enable; w(0) := e_in.write_cr_enable;
x := "" & (e_in.write_enable and e_in.rc); x(0) := (e_in.write_enable and e_in.rc);
assert (to_integer(unsigned(w)) + to_integer(unsigned(x))) <= 1 severity failure; assert (to_integer(unsigned(w)) + to_integer(unsigned(x))) <= 1 severity failure;


w_out <= WritebackToRegisterFileInit; w_out <= WritebackToRegisterFileInit;

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