From 0de83edf2e64ff73a7145cc6c01a5a0290b0c6a8 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Thu, 23 Jan 2020 11:37:24 +1100 Subject: [PATCH 1/2] Fix a Diamond build issue in writeback Diamond doesn't like the "" & method of converting std_logic to a single bit std_logic_vector. Thanks to Olof Kindgren for this patch. Signed-off-by: Anton Blanchard --- writeback.vhdl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/writeback.vhdl b/writeback.vhdl index e53f46b..a730266 100644 --- a/writeback.vhdl +++ b/writeback.vhdl @@ -64,16 +64,16 @@ begin variable zero : std_ulogic; variable sign : std_ulogic; begin - x := "" & e_in.valid; - y := "" & l_in.valid; + x(0) := e_in.valid; + y(0) := l_in.valid; assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure; - x := "" & e_in.write_enable; - y := "" & l_in.write_enable; + x(0) := e_in.write_enable; + y(0) := l_in.write_enable; assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure; - w := "" & e_in.write_cr_enable; - x := "" & (e_in.write_enable and e_in.rc); + w(0) := e_in.write_cr_enable; + x(0) := (e_in.write_enable and e_in.rc); assert (to_integer(unsigned(w)) + to_integer(unsigned(x))) <= 1 severity failure; w_out <= WritebackToRegisterFileInit; From 098f10136d9a507869b258dfae762996c7f0721d Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Thu, 23 Jan 2020 11:43:25 +1100 Subject: [PATCH 2/2] Fix a Diamond issue in decode2 By using a temporary we avoid a build issue in Diamond. Signed-off-by: Anton Blanchard --- decode2.vhdl | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/decode2.vhdl b/decode2.vhdl index 582fa5b..3d6b7d8 100644 --- a/decode2.vhdl +++ b/decode2.vhdl @@ -79,32 +79,33 @@ architecture behaviour of decode2 is function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0); reg_data : std_ulogic_vector(63 downto 0); ispr : gspr_index_t) return decode_input_reg_t is + variable ret : decode_input_reg_t; begin case t is when RB => assert is_fast_spr(ispr) = '0' report "Decode B says GPR but ISPR says SPR:" & to_hstring(ispr) severity failure; - return ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data); + ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data); when CONST_UI => - return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64))); + ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64))); when CONST_SI => - return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64))); + ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64))); when CONST_SI_HI => - return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64))); + ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64))); when CONST_UI_HI => - return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64))); + ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64))); when CONST_LI => - return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64))); + ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64))); when CONST_BD => - return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64))); + ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64))); when CONST_DS => - return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64))); + ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64))); when CONST_M1 => - return ('0', (others => '0'), x"FFFFFFFFFFFFFFFF"); + ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF"); when CONST_SH => - return ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11)); + ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11)); when CONST_SH32 => - return ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11)); + ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11)); when SPR => -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR. -- If it's all 0, we don't treat it as a dependency as slow SPRs @@ -112,10 +113,12 @@ architecture behaviour of decode2 is assert is_fast_spr(ispr) = '1' or ispr = "000000" report "Decode B says SPR but ISPR is invalid:" & to_hstring(ispr) severity failure; - return (is_fast_spr(ispr), ispr, reg_data); + ret := (is_fast_spr(ispr), ispr, reg_data); when NONE => - return ('0', (others => '0'), (others => '0')); + ret := ('0', (others => '0'), (others => '0')); end case; + + return ret; end; function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);