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Reformat multiply code

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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
pull/63/head
Anton Blanchard 5 years ago committed by Anton Blanchard
parent 99dd4de54e
commit 8dd97fbe7f
1 changed files with 81 additions and 81 deletions
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162
multiply.vhdl
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@ -9,93 +9,93 @@ use work.ppc_fx_insns.all;
use work.crhelpers.all; use work.crhelpers.all;


entity multiply is entity multiply is
generic ( generic (
PIPELINE_DEPTH : natural := 2 PIPELINE_DEPTH : natural := 2
); );
port ( port (
clk : in std_logic; clk : in std_logic;


m_in : in Decode2ToMultiplyType; m_in : in Decode2ToMultiplyType;
m_out : out MultiplyToWritebackType m_out : out MultiplyToWritebackType
); );
end entity multiply; end entity multiply;


architecture behaviour of multiply is architecture behaviour of multiply is
signal m: Decode2ToMultiplyType; signal m: Decode2ToMultiplyType;


type multiply_pipeline_stage is record type multiply_pipeline_stage is record
valid : std_ulogic; valid : std_ulogic;
insn_type : insn_type_t; insn_type : insn_type_t;
data : signed(129 downto 0); data : signed(129 downto 0);
write_reg : std_ulogic_vector(4 downto 0); write_reg : std_ulogic_vector(4 downto 0);
rc : std_ulogic; rc : std_ulogic;
end record; end record;
constant MultiplyPipelineStageInit : multiply_pipeline_stage := (valid => '0', insn_type => OP_ILLEGAL, rc => '0', data => (others => '0'), others => (others => '0')); constant MultiplyPipelineStageInit : multiply_pipeline_stage := (valid => '0', insn_type => OP_ILLEGAL, rc => '0', data => (others => '0'), others => (others => '0'));


type multiply_pipeline_type is array(0 to PIPELINE_DEPTH-1) of multiply_pipeline_stage; type multiply_pipeline_type is array(0 to PIPELINE_DEPTH-1) of multiply_pipeline_stage;
constant MultiplyPipelineInit : multiply_pipeline_type := (others => MultiplyPipelineStageInit); constant MultiplyPipelineInit : multiply_pipeline_type := (others => MultiplyPipelineStageInit);


type reg_type is record type reg_type is record
multiply_pipeline : multiply_pipeline_type; multiply_pipeline : multiply_pipeline_type;
end record; end record;


signal r, rin : reg_type := (multiply_pipeline => MultiplyPipelineInit); signal r, rin : reg_type := (multiply_pipeline => MultiplyPipelineInit);
begin begin
multiply_0: process(clk) multiply_0: process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
m <= m_in; m <= m_in;
r <= rin; r <= rin;
end if; end if;
end process; end process;


multiply_1: process(all) multiply_1: process(all)
variable v : reg_type; variable v : reg_type;
variable d : std_ulogic_vector(129 downto 0); variable d : std_ulogic_vector(129 downto 0);
variable d2 : std_ulogic_vector(63 downto 0); variable d2 : std_ulogic_vector(63 downto 0);
begin begin
v := r; v := r;


m_out <= MultiplyToWritebackInit; m_out <= MultiplyToWritebackInit;


v.multiply_pipeline(0).valid := m.valid; v.multiply_pipeline(0).valid := m.valid;
v.multiply_pipeline(0).insn_type := m.insn_type; v.multiply_pipeline(0).insn_type := m.insn_type;
v.multiply_pipeline(0).data := signed(m.data1) * signed(m.data2); v.multiply_pipeline(0).data := signed(m.data1) * signed(m.data2);
v.multiply_pipeline(0).write_reg := m.write_reg; v.multiply_pipeline(0).write_reg := m.write_reg;
v.multiply_pipeline(0).rc := m.rc; v.multiply_pipeline(0).rc := m.rc;


loop_0: for i in 1 to PIPELINE_DEPTH-1 loop loop_0: for i in 1 to PIPELINE_DEPTH-1 loop
v.multiply_pipeline(i) := r.multiply_pipeline(i-1); v.multiply_pipeline(i) := r.multiply_pipeline(i-1);
end loop; end loop;


d := std_ulogic_vector(v.multiply_pipeline(PIPELINE_DEPTH-1).data); d := std_ulogic_vector(v.multiply_pipeline(PIPELINE_DEPTH-1).data);


case_0: case v.multiply_pipeline(PIPELINE_DEPTH-1).insn_type is case_0: case v.multiply_pipeline(PIPELINE_DEPTH-1).insn_type is
when OP_MUL_L64 => when OP_MUL_L64 =>
d2 := d(63 downto 0); d2 := d(63 downto 0);
when OP_MUL_H32 => when OP_MUL_H32 =>
d2 := d(63 downto 32) & d(63 downto 32); d2 := d(63 downto 32) & d(63 downto 32);
when OP_MUL_H64 => when OP_MUL_H64 =>
d2 := d(127 downto 64); d2 := d(127 downto 64);
when others => when others =>
--report "Illegal insn type in multiplier"; --report "Illegal insn type in multiplier";
d2 := (others => '0'); d2 := (others => '0');
end case; end case;


m_out.write_reg_data <= d2; m_out.write_reg_data <= d2;
m_out.write_reg_nr <= v.multiply_pipeline(PIPELINE_DEPTH-1).write_reg; m_out.write_reg_nr <= v.multiply_pipeline(PIPELINE_DEPTH-1).write_reg;


if v.multiply_pipeline(PIPELINE_DEPTH-1).valid = '1' then if v.multiply_pipeline(PIPELINE_DEPTH-1).valid = '1' then
m_out.valid <= '1'; m_out.valid <= '1';
m_out.write_reg_enable <= '1'; m_out.write_reg_enable <= '1';


if v.multiply_pipeline(PIPELINE_DEPTH-1).rc = '1' then if v.multiply_pipeline(PIPELINE_DEPTH-1).rc = '1' then
m_out.write_cr_enable <= '1'; m_out.write_cr_enable <= '1';
m_out.write_cr_mask <= num_to_fxm(0); m_out.write_cr_mask <= num_to_fxm(0);
m_out.write_cr_data <= ppc_cmpi('1', d2, x"0000") & x"0000000"; m_out.write_cr_data <= ppc_cmpi('1', d2, x"0000") & x"0000000";
end if; end if;
end if; end if;


rin <= v; rin <= v;
end process; end process;
end architecture behaviour; end architecture behaviour;

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