Merge 9303ae2c89 into 83dcfeabf8
Jacob Lifshay
1 year ago
committed by
GitHub
commit
28f68c7a7b
@ -1,11 +1,24 @@
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
void console_init(void);
|
||||
void console_set_irq_en(bool rx_irq, bool tx_irq);
|
||||
int getchar(void);
|
||||
bool console_havechar(void);
|
||||
int putchar(int c);
|
||||
int puts(const char *str);
|
||||
|
||||
#ifndef __USE_LIBC
|
||||
size_t strlen(const char *s);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -0,0 +1,18 @@
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
int usb_getchar(void);
|
||||
bool usb_havechar(void);
|
||||
int usb_putchar(int c);
|
||||
int usb_puts(const char *str);
|
||||
void usb_console_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -0,0 +1,239 @@
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "console.h"
|
||||
#include "liteuart_console.h"
|
||||
#include "microwatt_soc.h"
|
||||
#include "io.h"
|
||||
|
||||
#define UART_BAUDS 115200
|
||||
|
||||
static uint64_t uart_base;
|
||||
|
||||
/* From Linux liteuart.c */
|
||||
#define OFF_RXTX 0x00
|
||||
#define OFF_TXFULL 0x04
|
||||
#define OFF_RXEMPTY 0x08
|
||||
#define OFF_EV_STATUS 0x0c
|
||||
#define OFF_EV_PENDING 0x10
|
||||
#define OFF_EV_ENABLE 0x14
|
||||
|
||||
/* From litex uart.h */
|
||||
#define UART_EV_TX 0x1
|
||||
#define UART_EV_RX 0x2
|
||||
|
||||
/* Modified version of csr.h */
|
||||
/* uart */
|
||||
static inline uint32_t uart_rxtx_read(void) {
|
||||
return readl(uart_base + OFF_RXTX);
|
||||
}
|
||||
|
||||
static inline void uart_rxtx_write(uint32_t v) {
|
||||
writel(v, uart_base + OFF_RXTX);
|
||||
}
|
||||
|
||||
static inline uint32_t uart_txfull_read(void) {
|
||||
return readl(uart_base + OFF_TXFULL);
|
||||
}
|
||||
|
||||
static inline uint32_t uart_rxempty_read(void) {
|
||||
return readl(uart_base + OFF_RXEMPTY);
|
||||
}
|
||||
|
||||
static inline uint32_t uart_ev_status_read(void) {
|
||||
return readl(uart_base + OFF_EV_STATUS);
|
||||
}
|
||||
|
||||
// static inline uint32_t uart_ev_status_tx_extract(uint32_t oldword) {
|
||||
// uint32_t mask = ((1 << 1)-1);
|
||||
// return ( (oldword >> 0) & mask );
|
||||
// }
|
||||
// static inline uint32_t uart_ev_status_tx_read(void) {
|
||||
// uint32_t word = uart_ev_status_read();
|
||||
// return uart_ev_status_tx_extract(word);
|
||||
// }
|
||||
|
||||
// static inline uint32_t uart_ev_status_rx_extract(uint32_t oldword) {
|
||||
// uint32_t mask = ((1 << 1)-1);
|
||||
// return ( (oldword >> 1) & mask );
|
||||
// }
|
||||
// static inline uint32_t uart_ev_status_rx_read(void) {
|
||||
// uint32_t word = uart_ev_status_read();
|
||||
// return uart_ev_status_rx_extract(word);
|
||||
// }
|
||||
|
||||
static inline uint32_t uart_ev_pending_read(void) {
|
||||
return readl(uart_base + OFF_EV_PENDING);
|
||||
}
|
||||
static inline void uart_ev_pending_write(uint32_t v) {
|
||||
writel(v, uart_base + OFF_EV_PENDING);
|
||||
}
|
||||
|
||||
// static inline uint32_t uart_ev_pending_tx_extract(uint32_t oldword) {
|
||||
// uint32_t mask = ((1 << 1)-1);
|
||||
// return ( (oldword >> 0) & mask );
|
||||
// }
|
||||
// static inline uint32_t uart_ev_pending_tx_read(void) {
|
||||
// uint32_t word = uart_ev_pending_read();
|
||||
// return uart_ev_pending_tx_extract(word);
|
||||
// }
|
||||
// static inline uint32_t uart_ev_pending_tx_replace(uint32_t oldword, uint32_t plain_value) {
|
||||
// uint32_t mask = ((1 << 1)-1);
|
||||
// return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
|
||||
// }
|
||||
// static inline void uart_ev_pending_tx_write(uint32_t plain_value) {
|
||||
// uint32_t oldword = uart_ev_pending_read();
|
||||
// uint32_t newword = uart_ev_pending_tx_replace(oldword, plain_value);
|
||||
// uart_ev_pending_write(newword);
|
||||
// }
|
||||
// #define CSR_UART_EV_PENDING_RX_OFFSET 1
|
||||
// #define CSR_UART_EV_PENDING_RX_SIZE 1
|
||||
// static inline uint32_t uart_ev_pending_rx_extract(uint32_t oldword) {
|
||||
// uint32_t mask = ((1 << 1)-1);
|
||||
// return ( (oldword >> 1) & mask );
|
||||
// }
|
||||
// static inline uint32_t uart_ev_pending_rx_read(void) {
|
||||
// uint32_t word = uart_ev_pending_read();
|
||||
// return uart_ev_pending_rx_extract(word);
|
||||
// }
|
||||
// static inline uint32_t uart_ev_pending_rx_replace(uint32_t oldword, uint32_t plain_value) {
|
||||
// uint32_t mask = ((1 << 1)-1);
|
||||
// return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
|
||||
// }
|
||||
// static inline void uart_ev_pending_rx_write(uint32_t plain_value) {
|
||||
// uint32_t oldword = uart_ev_pending_read();
|
||||
// uint32_t newword = uart_ev_pending_rx_replace(oldword, plain_value);
|
||||
// uart_ev_pending_write(newword);
|
||||
// }
|
||||
// #define CSR_UART_EV_ENABLE_ADDR (CSR_BASE + 0x814L)
|
||||
// #define CSR_UART_EV_ENABLE_SIZE 1
|
||||
// static inline uint32_t uart_ev_enable_read(void) {
|
||||
// return csr_read_simple(CSR_BASE + 0x814L);
|
||||
// }
|
||||
static inline void uart_ev_enable_write(uint32_t v) {
|
||||
writel(v, uart_base + OFF_EV_ENABLE);
|
||||
}
|
||||
// #define CSR_UART_EV_ENABLE_TX_OFFSET 0
|
||||
// #define CSR_UART_EV_ENABLE_TX_SIZE 1
|
||||
// static inline uint32_t uart_ev_enable_tx_extract(uint32_t oldword) {
|
||||
// uint32_t mask = ((1 << 1)-1);
|
||||
// return ( (oldword >> 0) & mask );
|
||||
// }
|
||||
// static inline uint32_t uart_ev_enable_tx_read(void) {
|
||||
// uint32_t word = uart_ev_enable_read();
|
||||
// return uart_ev_enable_tx_extract(word);
|
||||
// }
|
||||
// static inline uint32_t uart_ev_enable_tx_replace(uint32_t oldword, uint32_t plain_value) {
|
||||
// uint32_t mask = ((1 << 1)-1);
|
||||
// return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
|
||||
// }
|
||||
// static inline void uart_ev_enable_tx_write(uint32_t plain_value) {
|
||||
// uint32_t oldword = uart_ev_enable_read();
|
||||
// uint32_t newword = uart_ev_enable_tx_replace(oldword, plain_value);
|
||||
// uart_ev_enable_write(newword);
|
||||
// }
|
||||
// #define CSR_UART_EV_ENABLE_RX_OFFSET 1
|
||||
// #define CSR_UART_EV_ENABLE_RX_SIZE 1
|
||||
// static inline uint32_t uart_ev_enable_rx_extract(uint32_t oldword) {
|
||||
// uint32_t mask = ((1 << 1)-1);
|
||||
// return ( (oldword >> 1) & mask );
|
||||
// }
|
||||
// static inline uint32_t uart_ev_enable_rx_read(void) {
|
||||
// uint32_t word = uart_ev_enable_read();
|
||||
// return uart_ev_enable_rx_extract(word);
|
||||
// }
|
||||
// static inline uint32_t uart_ev_enable_rx_replace(uint32_t oldword, uint32_t plain_value) {
|
||||
// uint32_t mask = ((1 << 1)-1);
|
||||
// return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
|
||||
// }
|
||||
// static inline void uart_ev_enable_rx_write(uint32_t plain_value) {
|
||||
// uint32_t oldword = uart_ev_enable_read();
|
||||
// uint32_t newword = uart_ev_enable_rx_replace(oldword, plain_value);
|
||||
// uart_ev_enable_write(newword);
|
||||
// }
|
||||
// #define CSR_UART_TUNING_WORD_ADDR (CSR_BASE + 0x818L)
|
||||
// #define CSR_UART_TUNING_WORD_SIZE 1
|
||||
// static inline uint32_t uart_tuning_word_read(void) {
|
||||
// return csr_read_simple(CSR_BASE + 0x818L);
|
||||
// }
|
||||
// static inline void uart_tuning_word_write(uint32_t v) {
|
||||
// csr_write_simple(v, CSR_BASE + 0x818L);
|
||||
// }
|
||||
// #define CSR_UART_CONFIGURED_ADDR (CSR_BASE + 0x81cL)
|
||||
// #define CSR_UART_CONFIGURED_SIZE 1
|
||||
// static inline uint32_t uart_configured_read(void) {
|
||||
// return csr_read_simple(CSR_BASE + 0x81cL);
|
||||
// }
|
||||
// static inline void uart_configured_write(uint32_t v) {
|
||||
// csr_write_simple(v, CSR_BASE + 0x81cL);
|
||||
// }
|
||||
|
||||
// end of csr code
|
||||
|
||||
static char uart_read(void)
|
||||
{
|
||||
char c;
|
||||
while (uart_rxempty_read());
|
||||
c = uart_rxtx_read();
|
||||
uart_ev_pending_write(UART_EV_RX);
|
||||
return c;
|
||||
}
|
||||
|
||||
static int uart_read_nonblock(void)
|
||||
{
|
||||
return (uart_rxempty_read() == 0);
|
||||
}
|
||||
|
||||
static void uart_write(char c)
|
||||
{
|
||||
while (uart_txfull_read());
|
||||
uart_rxtx_write(c);
|
||||
uart_ev_pending_write(UART_EV_TX);
|
||||
}
|
||||
|
||||
static void uart_init(void)
|
||||
{
|
||||
uart_ev_pending_write(uart_ev_pending_read());
|
||||
uart_ev_enable_write(UART_EV_TX | UART_EV_RX);
|
||||
}
|
||||
|
||||
// static void uart_sync(void)
|
||||
// {
|
||||
// while (uart_txfull_read());
|
||||
// }
|
||||
|
||||
int usb_getchar(void)
|
||||
{
|
||||
return uart_read();
|
||||
}
|
||||
|
||||
bool usb_havechar(void)
|
||||
{
|
||||
return uart_read_nonblock();
|
||||
}
|
||||
|
||||
int usb_putchar(int c)
|
||||
{
|
||||
uart_write(c);
|
||||
return c;
|
||||
}
|
||||
|
||||
int usb_puts(const char *str)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; *str; i++) {
|
||||
char c = *(str++);
|
||||
if (c == 10)
|
||||
usb_putchar(13);
|
||||
usb_putchar(c);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void usb_console_init(void)
|
||||
{
|
||||
uart_base = UARTUSB_BASE;
|
||||
uart_init();
|
||||
}
|
||||
|
||||
@ -0,0 +1,6 @@
|
||||
usb_3d_game_emu
|
||||
*.o
|
||||
*.elf
|
||||
*.hex
|
||||
*.bin
|
||||
|
||||
@ -0,0 +1,44 @@
|
||||
ARCH = $(shell uname -m)
|
||||
ifneq ("$(ARCH)", "ppc64")
|
||||
ifneq ("$(ARCH)", "ppc64le")
|
||||
CROSS_COMPILE ?= powerpc64le-linux-gnu-
|
||||
endif
|
||||
endif
|
||||
|
||||
CC = $(CROSS_COMPILE)gcc
|
||||
CXX = $(CROSS_COMPILE)g++
|
||||
LD = $(CROSS_COMPILE)ld
|
||||
OBJCOPY = $(CROSS_COMPILE)objcopy
|
||||
|
||||
COMMON_FLAGS = -Os -g -Wall -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -I../include
|
||||
COMMON_FLAGS += -Werror -Wextra
|
||||
CXXFLAGS = $(COMMON_FLAGS) -std=c++14 -fno-exceptions
|
||||
CFLAGS = $(COMMON_FLAGS) -std=c99
|
||||
ASFLAGS = $(CFLAGS)
|
||||
LDFLAGS = -T powerpc.lds
|
||||
|
||||
all: usb_3d_game.hex
|
||||
|
||||
console.o: ../lib/console.c
|
||||
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@
|
||||
|
||||
liteuart_console.o: ../lib/liteuart_console.c
|
||||
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@
|
||||
|
||||
usb_3d_game.elf: usb_3d_game.o head.o console.o liteuart_console.o
|
||||
$(LD) $(LDFLAGS) -o $@ $^
|
||||
|
||||
usb_3d_game.bin: usb_3d_game.elf
|
||||
$(OBJCOPY) -O binary $^ $@
|
||||
|
||||
usb_3d_game.hex: usb_3d_game.bin
|
||||
../scripts/bin2hex.py $^ > $@
|
||||
|
||||
usb_3d_game_emu: usb_3d_game.cpp
|
||||
c++ -g -Wall -std=c++14 -Werror -Wextra -o usb_3d_game_emu usb_3d_game.cpp -DEMULATE_TARGET
|
||||
|
||||
clean:
|
||||
@rm -f *.o usb_3d_game.elf usb_3d_game.bin usb_3d_game.hex usb_3d_game_emu
|
||||
distclean: clean
|
||||
rm -f *~
|
||||
|
||||
@ -0,0 +1,39 @@
|
||||
# 3D Maze Game
|
||||
|
||||
Based on: <https://github.com/programmerjake/rv32/tree/v0.1.0.1-alpha/software>
|
||||
|
||||
# Run without FPGA/hardware-simulation
|
||||
|
||||
Resize your terminal to be at least 100x76.
|
||||
|
||||
Building:
|
||||
```bash
|
||||
cd usb_3d_game
|
||||
make usb_3d_game_emu
|
||||
```
|
||||
|
||||
Running:
|
||||
```bash
|
||||
./usb_3d_game_emu
|
||||
```
|
||||
|
||||
# Run on OrangeCrab v0.2.1
|
||||
|
||||
Set the OrangeCrab into firmware upload mode by plugging it in to USB while the button is pressed, then run the following commands:
|
||||
|
||||
Building/Flashing:
|
||||
```bash
|
||||
(cd usb_3d_game; make)
|
||||
sudo make FPGA_TARGET=ORANGE-CRAB-0.21 dfuprog DOCKER=1 LITEDRAM_GHDL_ARG=-gUSE_LITEDRAM=false RAM_INIT_FILE=usb_3d_game/usb_3d_game.hex MEMORY_SIZE=$((1<<18))
|
||||
```
|
||||
|
||||
Then, in a separate terminal that you've resized to be at least 100x76, run (replacing ttyACM0 with whatever serial device the OrangeCrab is):
|
||||
```bash
|
||||
sudo tio /dev/ttyACM0
|
||||
```
|
||||
|
||||
# Controls
|
||||
|
||||
Use WASD or the Arrow keys to move around. Press Ctrl+C to quit or restart.
|
||||
|
||||
The goal is a set of flashing blocks, nothing special yet happens when you reach them though.
|
||||
@ -0,0 +1,107 @@
|
||||
/* Copyright 2013-2014 IBM Corp.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
|
||||
* implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#define STACK_TOP 0x20000
|
||||
|
||||
#define FIXUP_ENDIAN \
|
||||
tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
|
||||
b 191f; /* Skip trampoline if endian is good */ \
|
||||
.long 0xa600607d; /* mfmsr r11 */ \
|
||||
.long 0x01006b69; /* xori r11,r11,1 */ \
|
||||
.long 0x05009f42; /* bcl 20,31,$+4 */ \
|
||||
.long 0xa602487d; /* mflr r10 */ \
|
||||
.long 0x14004a39; /* addi r10,r10,20 */ \
|
||||
.long 0xa64b5a7d; /* mthsrr0 r10 */ \
|
||||
.long 0xa64b7b7d; /* mthsrr1 r11 */ \
|
||||
.long 0x2402004c; /* hrfid */ \
|
||||
191:
|
||||
|
||||
|
||||
/* Load an immediate 64-bit value into a register */
|
||||
#define LOAD_IMM64(r, e) \
|
||||
lis r,(e)@highest; \
|
||||
ori r,r,(e)@higher; \
|
||||
rldicr r,r, 32, 31; \
|
||||
oris r,r, (e)@h; \
|
||||
ori r,r, (e)@l;
|
||||
|
||||
.section ".head","ax"
|
||||
|
||||
/*
|
||||
* Microwatt currently enters in LE mode at 0x0, so we don't need to
|
||||
* do any endian fix ups>
|
||||
*/
|
||||
. = 0
|
||||
.global _start
|
||||
_start:
|
||||
b boot_entry
|
||||
|
||||
/* QEMU enters at 0x10 */
|
||||
. = 0x10
|
||||
FIXUP_ENDIAN
|
||||
b boot_entry
|
||||
|
||||
. = 0x100
|
||||
FIXUP_ENDIAN
|
||||
b boot_entry
|
||||
|
||||
.global boot_entry
|
||||
boot_entry:
|
||||
/* setup stack */
|
||||
LOAD_IMM64(%r1, STACK_TOP - 0x100)
|
||||
LOAD_IMM64(%r12, main)
|
||||
mtctr %r12,
|
||||
bctrl
|
||||
b .
|
||||
|
||||
#define EXCEPTION(nr) \
|
||||
.= nr ;\
|
||||
b .
|
||||
|
||||
/* More exception stubs */
|
||||
EXCEPTION(0x300)
|
||||
EXCEPTION(0x380)
|
||||
EXCEPTION(0x400)
|
||||
EXCEPTION(0x480)
|
||||
EXCEPTION(0x500)
|
||||
EXCEPTION(0x600)
|
||||
EXCEPTION(0x700)
|
||||
EXCEPTION(0x800)
|
||||
EXCEPTION(0x900)
|
||||
EXCEPTION(0x980)
|
||||
EXCEPTION(0xa00)
|
||||
EXCEPTION(0xb00)
|
||||
EXCEPTION(0xc00)
|
||||
EXCEPTION(0xd00)
|
||||
EXCEPTION(0xe00)
|
||||
EXCEPTION(0xe20)
|
||||
EXCEPTION(0xe40)
|
||||
EXCEPTION(0xe60)
|
||||
EXCEPTION(0xe80)
|
||||
EXCEPTION(0xf00)
|
||||
EXCEPTION(0xf20)
|
||||
EXCEPTION(0xf40)
|
||||
EXCEPTION(0xf60)
|
||||
EXCEPTION(0xf80)
|
||||
#if 0
|
||||
EXCEPTION(0x1000)
|
||||
EXCEPTION(0x1100)
|
||||
EXCEPTION(0x1200)
|
||||
EXCEPTION(0x1300)
|
||||
EXCEPTION(0x1400)
|
||||
EXCEPTION(0x1500)
|
||||
EXCEPTION(0x1600)
|
||||
#endif
|
||||
@ -0,0 +1,13 @@
|
||||
SECTIONS
|
||||
{
|
||||
. = 0;
|
||||
.head : {
|
||||
KEEP(*(.head))
|
||||
}
|
||||
. = 0x1000;
|
||||
.text : { *(.text) }
|
||||
. = 0x2a000;
|
||||
.data : { *(.data) }
|
||||
.rodata : { *(.rodata) }
|
||||
.bss : { *(.bss) }
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,38 @@
|
||||
ARCH = $(shell uname -m)
|
||||
ifneq ("$(ARCH)", "ppc64")
|
||||
ifneq ("$(ARCH)", "ppc64le")
|
||||
CROSS_COMPILE ?= powerpc64le-linux-gnu-
|
||||
endif
|
||||
endif
|
||||
|
||||
CC = $(CROSS_COMPILE)gcc
|
||||
LD = $(CROSS_COMPILE)ld
|
||||
OBJCOPY = $(CROSS_COMPILE)objcopy
|
||||
|
||||
CFLAGS = -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -I../include
|
||||
CFLAGS += -Werror -Wextra
|
||||
ASFLAGS = $(CFLAGS)
|
||||
LDFLAGS = -T powerpc.lds
|
||||
|
||||
all: usb_hello.hex
|
||||
|
||||
console.o: ../lib/console.c
|
||||
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@
|
||||
|
||||
liteuart_console.o: ../lib/liteuart_console.c
|
||||
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@
|
||||
|
||||
usb_hello.elf: usb_hello.o head.o console.o liteuart_console.o
|
||||
$(LD) $(LDFLAGS) -o $@ $^
|
||||
|
||||
usb_hello.bin: usb_hello.elf
|
||||
$(OBJCOPY) -O binary $^ $@
|
||||
|
||||
usb_hello.hex: usb_hello.bin
|
||||
../scripts/bin2hex.py $^ > $@
|
||||
|
||||
clean:
|
||||
@rm -f *.o usb_hello.elf usb_hello.bin usb_hello.hex
|
||||
distclean: clean
|
||||
rm -f *~
|
||||
|
||||
@ -0,0 +1,107 @@
|
||||
/* Copyright 2013-2014 IBM Corp.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
|
||||
* implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#define STACK_TOP 0x2000
|
||||
|
||||
#define FIXUP_ENDIAN \
|
||||
tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
|
||||
b 191f; /* Skip trampoline if endian is good */ \
|
||||
.long 0xa600607d; /* mfmsr r11 */ \
|
||||
.long 0x01006b69; /* xori r11,r11,1 */ \
|
||||
.long 0x05009f42; /* bcl 20,31,$+4 */ \
|
||||
.long 0xa602487d; /* mflr r10 */ \
|
||||
.long 0x14004a39; /* addi r10,r10,20 */ \
|
||||
.long 0xa64b5a7d; /* mthsrr0 r10 */ \
|
||||
.long 0xa64b7b7d; /* mthsrr1 r11 */ \
|
||||
.long 0x2402004c; /* hrfid */ \
|
||||
191:
|
||||
|
||||
|
||||
/* Load an immediate 64-bit value into a register */
|
||||
#define LOAD_IMM64(r, e) \
|
||||
lis r,(e)@highest; \
|
||||
ori r,r,(e)@higher; \
|
||||
rldicr r,r, 32, 31; \
|
||||
oris r,r, (e)@h; \
|
||||
ori r,r, (e)@l;
|
||||
|
||||
.section ".head","ax"
|
||||
|
||||
/*
|
||||
* Microwatt currently enters in LE mode at 0x0, so we don't need to
|
||||
* do any endian fix ups>
|
||||
*/
|
||||
. = 0
|
||||
.global _start
|
||||
_start:
|
||||
b boot_entry
|
||||
|
||||
/* QEMU enters at 0x10 */
|
||||
. = 0x10
|
||||
FIXUP_ENDIAN
|
||||
b boot_entry
|
||||
|
||||
. = 0x100
|
||||
FIXUP_ENDIAN
|
||||
b boot_entry
|
||||
|
||||
.global boot_entry
|
||||
boot_entry:
|
||||
/* setup stack */
|
||||
LOAD_IMM64(%r1, STACK_TOP - 0x100)
|
||||
LOAD_IMM64(%r12, main)
|
||||
mtctr %r12,
|
||||
bctrl
|
||||
b .
|
||||
|
||||
#define EXCEPTION(nr) \
|
||||
.= nr ;\
|
||||
b .
|
||||
|
||||
/* More exception stubs */
|
||||
EXCEPTION(0x300)
|
||||
EXCEPTION(0x380)
|
||||
EXCEPTION(0x400)
|
||||
EXCEPTION(0x480)
|
||||
EXCEPTION(0x500)
|
||||
EXCEPTION(0x600)
|
||||
EXCEPTION(0x700)
|
||||
EXCEPTION(0x800)
|
||||
EXCEPTION(0x900)
|
||||
EXCEPTION(0x980)
|
||||
EXCEPTION(0xa00)
|
||||
EXCEPTION(0xb00)
|
||||
EXCEPTION(0xc00)
|
||||
EXCEPTION(0xd00)
|
||||
EXCEPTION(0xe00)
|
||||
EXCEPTION(0xe20)
|
||||
EXCEPTION(0xe40)
|
||||
EXCEPTION(0xe60)
|
||||
EXCEPTION(0xe80)
|
||||
EXCEPTION(0xf00)
|
||||
EXCEPTION(0xf20)
|
||||
EXCEPTION(0xf40)
|
||||
EXCEPTION(0xf60)
|
||||
EXCEPTION(0xf80)
|
||||
#if 0
|
||||
EXCEPTION(0x1000)
|
||||
EXCEPTION(0x1100)
|
||||
EXCEPTION(0x1200)
|
||||
EXCEPTION(0x1300)
|
||||
EXCEPTION(0x1400)
|
||||
EXCEPTION(0x1500)
|
||||
EXCEPTION(0x1600)
|
||||
#endif
|
||||
@ -0,0 +1,12 @@
|
||||
SECTIONS
|
||||
{
|
||||
. = 0;
|
||||
.head : {
|
||||
KEEP(*(.head))
|
||||
}
|
||||
. = 0x1000;
|
||||
.text : { *(.text) }
|
||||
. = 0x2a00;
|
||||
.data : { *(.data) }
|
||||
.bss : { *(.bss) }
|
||||
}
|
||||
@ -0,0 +1,72 @@
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "console.h"
|
||||
#include "liteuart_console.h"
|
||||
|
||||
#include "microwatt_soc.h"
|
||||
#include "io.h"
|
||||
|
||||
static char mw_logo[] =
|
||||
|
||||
"\n"
|
||||
" .oOOo. \n"
|
||||
" .\" \". \n"
|
||||
" ; .mw. ; Microwatt, it works.\n"
|
||||
" . ' ' . \n"
|
||||
" \\ || / \n"
|
||||
" ;..; \n"
|
||||
" ;..; \n"
|
||||
" `ww' \n";
|
||||
|
||||
static void print_hex(unsigned long val, int ndigits)
|
||||
{
|
||||
int i, x;
|
||||
|
||||
for (i = (ndigits - 1) * 4; i >= 0; i -= 4) {
|
||||
x = (val >> i) & 0xf;
|
||||
if (x >= 10)
|
||||
putchar(x + 'a' - 10);
|
||||
else
|
||||
putchar(x + '0');
|
||||
}
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
console_init();
|
||||
usb_console_init();
|
||||
|
||||
puts(mw_logo);
|
||||
|
||||
for (int i = 0; i <= 0x14; i+=4) {
|
||||
unsigned long val = readl(UART0_BASE + i);
|
||||
puts("reg 0x");
|
||||
print_hex(i, 2);
|
||||
puts(" = 0x");
|
||||
print_hex(val, 8);
|
||||
puts("\n");
|
||||
}
|
||||
puts("printed\n");
|
||||
for (int i = 0; i <= 0x14; i+=4) {
|
||||
unsigned long val = readl(UART0_BASE + i);
|
||||
puts("reg 0x");
|
||||
print_hex(i, 2);
|
||||
puts(" = 0x");
|
||||
print_hex(val, 8);
|
||||
puts("\n");
|
||||
}
|
||||
puts("printed\n");
|
||||
|
||||
usb_puts(mw_logo);
|
||||
|
||||
while (1) {
|
||||
// puts(mw_logo);
|
||||
// usb_puts(mw_logo);
|
||||
unsigned char c = usb_getchar();
|
||||
putchar(c);
|
||||
usb_putchar(c);
|
||||
if (c == 13) // if CR send LF
|
||||
putchar(10);
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,263 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
# Based on valentyusb/sim/generate_verilog.py , modified
|
||||
# for Microwatt
|
||||
|
||||
# This variable defines all the external programs that this module
|
||||
# relies on. lxbuildenv reads this variable in order to ensure
|
||||
# the build will finish without exiting due to missing third-party
|
||||
# programs.
|
||||
LX_DEPENDENCIES = []
|
||||
|
||||
# Import lxbuildenv to integrate the deps/ directory
|
||||
#import lxbuildenv
|
||||
|
||||
# Disable pylint's E1101, which breaks completely on migen
|
||||
#pylint:disable=E1101
|
||||
|
||||
import argparse
|
||||
import os
|
||||
import yaml
|
||||
|
||||
#from migen import *
|
||||
from migen import Module, Signal, Instance, ClockDomain, If
|
||||
from migen.genlib.resetsync import AsyncResetSynchronizer
|
||||
from migen.fhdl.specials import TSTriple
|
||||
from migen.fhdl.bitcontainer import bits_for
|
||||
from migen.fhdl.structure import ClockSignal, ResetSignal, Replicate, Cat
|
||||
|
||||
# from litex.build.sim.platform import SimPlatform
|
||||
from litex.build.lattice import LatticePlatform
|
||||
from litex.build.generic_platform import Pins, IOStandard, Misc, Subsignal
|
||||
from litex.soc.integration.soc_core import SoCCore
|
||||
from litex.soc.integration.builder import Builder
|
||||
from litex.soc.interconnect import wishbone
|
||||
from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
|
||||
|
||||
from valentyusb import usbcore
|
||||
from valentyusb.usbcore import io as usbio
|
||||
from valentyusb.usbcore.cpu import dummyusb, cdc_eptri, eptri, epfifo
|
||||
from valentyusb.usbcore.endpoint import EndpointType
|
||||
|
||||
_connectors = []
|
||||
|
||||
class _CRG(Module):
|
||||
def __init__(self, platform):
|
||||
clk = platform.request("clk")
|
||||
rst = platform.request("reset")
|
||||
|
||||
clk12 = Signal()
|
||||
|
||||
self.clock_domains.cd_sys = ClockDomain()
|
||||
self.clock_domains.cd_usb_12 = ClockDomain()
|
||||
self.clock_domains.cd_usb_48 = ClockDomain()
|
||||
self.clock_domains.cd_usb_48_to_12 = ClockDomain()
|
||||
|
||||
clk48 = clk.clk48
|
||||
|
||||
self.comb += self.cd_usb_48.clk.eq(clk48)
|
||||
self.comb += self.cd_usb_48_to_12.clk.eq(clk48)
|
||||
|
||||
clk12_counter = Signal(2)
|
||||
self.sync.usb_48_to_12 += clk12_counter.eq(clk12_counter + 1)
|
||||
|
||||
self.comb += clk12.eq(clk12_counter[1])
|
||||
|
||||
self.comb += self.cd_sys.clk.eq(clk.clksys)
|
||||
self.comb += self.cd_usb_12.clk.eq(clk12)
|
||||
|
||||
self.comb += [
|
||||
ResetSignal("sys").eq(rst),
|
||||
ResetSignal("usb_12").eq(rst),
|
||||
ResetSignal("usb_48").eq(rst),
|
||||
]
|
||||
|
||||
class BaseSoC(SoCCore):
|
||||
|
||||
def __init__(self, platform, io, sys_freq, output_dir="build", usb_variant='dummy', **kwargs):
|
||||
# Disable integrated RAM as we'll add it later
|
||||
self.integrated_sram_size = 0
|
||||
|
||||
self.output_dir = output_dir
|
||||
|
||||
platform.add_extension(io)
|
||||
|
||||
self.submodules.crg = _CRG(platform)
|
||||
|
||||
# prior to SocCore.__init__
|
||||
self.csr_map = {
|
||||
"uart": 0, # microwatt soc will remap addresses to 0
|
||||
}
|
||||
|
||||
SoCCore.__init__(self, platform, sys_freq,
|
||||
cpu_type=None,
|
||||
integrated_rom_size=0x0,
|
||||
integrated_sram_size=0x0,
|
||||
integrated_main_ram_size=0x0,
|
||||
csr_address_width=14, csr_data_width=32,
|
||||
with_uart=False, with_timer=False)
|
||||
|
||||
# Add USB pads
|
||||
usb_pads = platform.request("usb")
|
||||
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
|
||||
self.comb += usb_pads.tx_en.eq(usb_iobuf.usb_tx_en)
|
||||
if usb_variant == 'eptri':
|
||||
self.submodules.usb = eptri.TriEndpointInterface(usb_iobuf, debug=True)
|
||||
elif usb_variant == 'epfifo':
|
||||
self.submodules.usb = epfifo.PerEndpointFifoInterface(usb_iobuf, debug=True)
|
||||
elif usb_variant == 'cdc_eptri':
|
||||
extra_args = {}
|
||||
passthrough = ['product', 'manufacturer']
|
||||
for p in passthrough:
|
||||
try:
|
||||
extra_args[p] = kwargs[p]
|
||||
except KeyError:
|
||||
pass
|
||||
self.submodules.uart = cdc_eptri.CDCUsb(usb_iobuf, debug=True, **extra_args)
|
||||
elif usb_variant == 'dummy':
|
||||
self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=True)
|
||||
else:
|
||||
raise ValueError('Invalid endpoints value. It is currently \'eptri\' and \'dummy\'')
|
||||
try:
|
||||
self.add_wb_master(self.usb.debug_bridge.wishbone)
|
||||
except AttributeError:
|
||||
pass
|
||||
|
||||
if self.uart:
|
||||
self.comb += self.platform.request("interrupt").eq(self.uart.ev.irq)
|
||||
|
||||
wb_ctrl = wishbone.Interface()
|
||||
self.add_wb_master(wb_ctrl)
|
||||
platform.add_extension(wb_ctrl.get_ios("wb_ctrl"))
|
||||
self.comb += wb_ctrl.connect_to_pads(self.platform.request("wishbone"), mode="slave")
|
||||
|
||||
def add_fsm_state_names():
|
||||
"""Hack the FSM module to add state names to the output"""
|
||||
from migen.fhdl.visit import NodeTransformer
|
||||
from migen.genlib.fsm import NextState, NextValue, _target_eq
|
||||
from migen.fhdl.bitcontainer import value_bits_sign
|
||||
|
||||
class My_LowerNext(NodeTransformer):
|
||||
def __init__(self, next_state_signal, next_state_name_signal, encoding, aliases):
|
||||
self.next_state_signal = next_state_signal
|
||||
self.next_state_name_signal = next_state_name_signal
|
||||
self.encoding = encoding
|
||||
self.aliases = aliases
|
||||
# (target, next_value_ce, next_value)
|
||||
self.registers = []
|
||||
|
||||
def _get_register_control(self, target):
|
||||
for x in self.registers:
|
||||
if _target_eq(target, x[0]):
|
||||
return x[1], x[2]
|
||||
raise KeyError
|
||||
|
||||
def visit_unknown(self, node):
|
||||
if isinstance(node, NextState):
|
||||
try:
|
||||
actual_state = self.aliases[node.state]
|
||||
except KeyError:
|
||||
actual_state = node.state
|
||||
return [
|
||||
self.next_state_signal.eq(self.encoding[actual_state]),
|
||||
self.next_state_name_signal.eq(int.from_bytes(actual_state.encode(), byteorder="big"))
|
||||
]
|
||||
elif isinstance(node, NextValue):
|
||||
try:
|
||||
next_value_ce, next_value = self._get_register_control(node.target)
|
||||
except KeyError:
|
||||
related = node.target if isinstance(node.target, Signal) else None
|
||||
next_value = Signal(bits_sign=value_bits_sign(node.target), related=related)
|
||||
next_value_ce = Signal(related=related)
|
||||
self.registers.append((node.target, next_value_ce, next_value))
|
||||
return next_value.eq(node.value), next_value_ce.eq(1)
|
||||
else:
|
||||
return node
|
||||
import migen.genlib.fsm as fsm
|
||||
def my_lower_controls(self):
|
||||
self.state_name = Signal(len(max(self.encoding,key=len))*8, reset=int.from_bytes(self.reset_state.encode(), byteorder="big"))
|
||||
self.next_state_name = Signal(len(max(self.encoding,key=len))*8, reset=int.from_bytes(self.reset_state.encode(), byteorder="big"))
|
||||
self.comb += self.next_state_name.eq(self.state_name)
|
||||
self.sync += self.state_name.eq(self.next_state_name)
|
||||
return My_LowerNext(self.next_state, self.next_state_name, self.encoding, self.state_aliases)
|
||||
fsm.FSM._lower_controls = my_lower_controls
|
||||
|
||||
|
||||
_io = [
|
||||
# Wishbone
|
||||
("wishbone", 0,
|
||||
Subsignal("adr", Pins(30)),
|
||||
Subsignal("dat_r", Pins(32)),
|
||||
Subsignal("dat_w", Pins(32)),
|
||||
Subsignal("sel", Pins(4)),
|
||||
Subsignal("cyc", Pins(1)),
|
||||
Subsignal("stb", Pins(1)),
|
||||
Subsignal("ack", Pins(1)),
|
||||
Subsignal("we", Pins(1)),
|
||||
Subsignal("cti", Pins(3)),
|
||||
Subsignal("bte", Pins(2)),
|
||||
Subsignal("err", Pins(1))
|
||||
),
|
||||
("usb", 0,
|
||||
Subsignal("d_p", Pins(1)),
|
||||
Subsignal("d_n", Pins(1)),
|
||||
Subsignal("pullup", Pins(1)),
|
||||
Subsignal("tx_en", Pins(1)),
|
||||
),
|
||||
("clk", 0,
|
||||
Subsignal("clk48", Pins(1)),
|
||||
Subsignal("clksys", Pins(1)),
|
||||
),
|
||||
("interrupt", 0, Pins(1)),
|
||||
("reset", 0, Pins(1)),
|
||||
]
|
||||
|
||||
def generate(core_config, output_dir, csr_csv):
|
||||
|
||||
toolchain = core_config["toolchain"]
|
||||
if toolchain == "trellis":
|
||||
platform = LatticePlatform(core_config["device"], [], toolchain=toolchain)
|
||||
else:
|
||||
raise ValueError(f"Unknown config toolchain {toolchain}")
|
||||
|
||||
soc = BaseSoC(platform, _io, core_config["sys_freq"],
|
||||
usb_variant=core_config["usb_variant"],
|
||||
cpu_type=None, cpu_variant=None,
|
||||
output_dir=output_dir,
|
||||
product=core_config["product"],
|
||||
manufacturer="Microwatt")
|
||||
builder = Builder(soc, output_dir=output_dir,
|
||||
csr_csv=csr_csv,
|
||||
compile_software=False)
|
||||
vns = builder.build(run=False, build_name='valentyusb')
|
||||
soc.do_exit(vns)
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(description="Build standalone ValentyUSB verilog output")
|
||||
# parser.add_argument('variant', metavar='VARIANT',
|
||||
# choices=['dummy', 'cdc_eptri', 'eptri', 'epfifo'],
|
||||
# default='dummy',
|
||||
# help='USB variant. Choices: [%(choices)s] (default: %(default)s)' )
|
||||
parser.add_argument('--dir', metavar='DIRECTORY',
|
||||
default='build',
|
||||
help='Output directory (default: %(default)s)' )
|
||||
parser.add_argument('--csr', metavar='CSR',
|
||||
default='csr.csv',
|
||||
help='csr file (default: %(default)s)')
|
||||
parser.add_argument('config', type=argparse.FileType('r'),
|
||||
help='Input platform config file')
|
||||
args = parser.parse_args()
|
||||
|
||||
core_config = yaml.load(args.config.read(), Loader=yaml.Loader)
|
||||
# XXX matt - not sure if this needed, maybe only for sim target?
|
||||
# add_fsm_state_names()
|
||||
output_dir = args.dir
|
||||
generate(core_config, output_dir, args.csr)
|
||||
|
||||
print(
|
||||
"""Build complete. Output files:
|
||||
{}/gateware/valentyusb.v Source Verilog file.
|
||||
""".format(output_dir))
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
@ -0,0 +1,15 @@
|
||||
#!/bin/sh
|
||||
|
||||
# This requires https://github.com/litex-hub/valentyusb branch hw_cdc_eptri
|
||||
# Tested with
|
||||
# commit 912d8e6dc72d45e092e608ffcaabfeaaa6d4580f
|
||||
# Date: Wed Jan 6 09:42:42 2021 +0100
|
||||
|
||||
set -e
|
||||
|
||||
GENSRCDIR=$(dirname $0)
|
||||
cd $GENSRCDIR
|
||||
|
||||
for b in orangecrab-85-0.2; do
|
||||
./generate.py --dir ../generated/$b $b.yml
|
||||
done
|
||||
@ -0,0 +1,7 @@
|
||||
{
|
||||
"device": "LFE5U-85F-8MG285C",
|
||||
"toolchain": "trellis",
|
||||
"usb_variant": "cdc_eptri",
|
||||
"sys_freq": 48000000,
|
||||
"product": "Microwatt on OrangeCrab",
|
||||
}
|
||||
@ -0,0 +1,5 @@
|
||||
# Autogenerated by LiteX / git: --------
|
||||
set -e
|
||||
yosys -l valentyusb.rpt valentyusb.ys
|
||||
nextpnr-ecp5 --json valentyusb.json --lpf valentyusb.lpf --textcfg valentyusb.config --85k --package CSFBGA285 --speed 8 --timing-allow-fail --seed 1
|
||||
ecppack valentyusb.config --svf valentyusb.svf --bit valentyusb.bit --bootaddr 0
|
||||
@ -0,0 +1,249 @@
|
||||
00
|
||||
09
|
||||
02
|
||||
3e
|
||||
00
|
||||
02
|
||||
01
|
||||
00
|
||||
80
|
||||
32
|
||||
09
|
||||
04
|
||||
00
|
||||
00
|
||||
01
|
||||
02
|
||||
02
|
||||
00
|
||||
00
|
||||
05
|
||||
24
|
||||
00
|
||||
10
|
||||
01
|
||||
04
|
||||
24
|
||||
02
|
||||
02
|
||||
05
|
||||
24
|
||||
06
|
||||
00
|
||||
01
|
||||
07
|
||||
05
|
||||
81
|
||||
03
|
||||
08
|
||||
00
|
||||
40
|
||||
09
|
||||
04
|
||||
01
|
||||
00
|
||||
02
|
||||
0a
|
||||
00
|
||||
00
|
||||
00
|
||||
07
|
||||
05
|
||||
02
|
||||
02
|
||||
40
|
||||
00
|
||||
00
|
||||
07
|
||||
05
|
||||
82
|
||||
02
|
||||
40
|
||||
00
|
||||
00
|
||||
12
|
||||
01
|
||||
00
|
||||
02
|
||||
02
|
||||
00
|
||||
00
|
||||
40
|
||||
09
|
||||
12
|
||||
f2
|
||||
5b
|
||||
01
|
||||
01
|
||||
01
|
||||
02
|
||||
00
|
||||
01
|
||||
04
|
||||
03
|
||||
09
|
||||
04
|
||||
14
|
||||
03
|
||||
4d
|
||||
00
|
||||
69
|
||||
00
|
||||
63
|
||||
00
|
||||
72
|
||||
00
|
||||
6f
|
||||
00
|
||||
77
|
||||
00
|
||||
61
|
||||
00
|
||||
74
|
||||
00
|
||||
74
|
||||
00
|
||||
30
|
||||
03
|
||||
4d
|
||||
00
|
||||
69
|
||||
00
|
||||
63
|
||||
00
|
||||
72
|
||||
00
|
||||
6f
|
||||
00
|
||||
77
|
||||
00
|
||||
61
|
||||
00
|
||||
74
|
||||
00
|
||||
74
|
||||
00
|
||||
20
|
||||
00
|
||||
6f
|
||||
00
|
||||
6e
|
||||
00
|
||||
20
|
||||
00
|
||||
4f
|
||||
00
|
||||
72
|
||||
00
|
||||
61
|
||||
00
|
||||
6e
|
||||
00
|
||||
67
|
||||
00
|
||||
65
|
||||
00
|
||||
43
|
||||
00
|
||||
72
|
||||
00
|
||||
61
|
||||
00
|
||||
62
|
||||
00
|
||||
05
|
||||
0f
|
||||
1d
|
||||
00
|
||||
01
|
||||
18
|
||||
10
|
||||
05
|
||||
00
|
||||
38
|
||||
b6
|
||||
08
|
||||
34
|
||||
a9
|
||||
09
|
||||
a0
|
||||
47
|
||||
8b
|
||||
fd
|
||||
a0
|
||||
76
|
||||
88
|
||||
15
|
||||
b6
|
||||
65
|
||||
00
|
||||
01
|
||||
02
|
||||
01
|
||||
12
|
||||
03
|
||||
4d
|
||||
53
|
||||
46
|
||||
54
|
||||
31
|
||||
30
|
||||
30
|
||||
7e
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
28
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
01
|
||||
04
|
||||
00
|
||||
01
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
01
|
||||
57
|
||||
49
|
||||
4e
|
||||
55
|
||||
53
|
||||
42
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
c2
|
||||
01
|
||||
00
|
||||
00
|
||||
00
|
||||
08
|
||||
@ -0,0 +1,118 @@
|
||||
BLOCK RESETPATHS;
|
||||
BLOCK ASYNCPATHS;
|
||||
LOCATE COMP "clk_clk48" SITE "X";
|
||||
LOCATE COMP "clk_clksys" SITE "X";
|
||||
LOCATE COMP "reset" SITE "X";
|
||||
LOCATE COMP "usb_d_p" SITE "X";
|
||||
LOCATE COMP "usb_d_n" SITE "X";
|
||||
LOCATE COMP "usb_pullup" SITE "X";
|
||||
LOCATE COMP "usb_tx_en" SITE "X";
|
||||
LOCATE COMP "interrupt" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[0]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[1]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[2]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[3]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[4]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[5]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[6]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[7]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[8]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[9]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[10]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[11]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[12]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[13]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[14]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[15]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[16]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[17]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[18]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[19]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[20]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[21]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[22]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[23]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[24]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[25]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[26]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[27]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[28]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[29]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[0]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[1]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[2]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[3]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[4]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[5]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[6]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[7]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[8]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[9]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[10]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[11]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[12]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[13]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[14]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[15]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[16]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[17]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[18]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[19]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[20]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[21]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[22]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[23]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[24]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[25]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[26]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[27]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[28]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[29]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[30]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[31]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[0]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[1]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[2]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[3]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[4]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[5]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[6]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[7]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[8]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[9]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[10]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[11]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[12]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[13]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[14]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[15]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[16]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[17]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[18]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[19]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[20]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[21]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[22]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[23]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[24]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[25]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[26]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[27]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[28]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[29]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[30]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[31]" SITE "X";
|
||||
LOCATE COMP "wishbone_sel[0]" SITE "X";
|
||||
LOCATE COMP "wishbone_sel[1]" SITE "X";
|
||||
LOCATE COMP "wishbone_sel[2]" SITE "X";
|
||||
LOCATE COMP "wishbone_sel[3]" SITE "X";
|
||||
LOCATE COMP "wishbone_cyc" SITE "X";
|
||||
LOCATE COMP "wishbone_stb" SITE "X";
|
||||
LOCATE COMP "wishbone_ack" SITE "X";
|
||||
LOCATE COMP "wishbone_we" SITE "X";
|
||||
LOCATE COMP "wishbone_cti[0]" SITE "X";
|
||||
LOCATE COMP "wishbone_cti[1]" SITE "X";
|
||||
LOCATE COMP "wishbone_cti[2]" SITE "X";
|
||||
LOCATE COMP "wishbone_bte[0]" SITE "X";
|
||||
LOCATE COMP "wishbone_bte[1]" SITE "X";
|
||||
LOCATE COMP "wishbone_err" SITE "X";
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,6 @@
|
||||
verilog_defaults -push
|
||||
verilog_defaults -add -defer
|
||||
read_verilog /home/matt/3rd/fpga/microwatt/valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.v
|
||||
verilog_defaults -pop
|
||||
attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0
|
||||
synth_ecp5 -json valentyusb.json -top valentyusb
|
||||
@ -0,0 +1,232 @@
|
||||
//--------------------------------------------------------------------------------
|
||||
// Auto-generated by Migen (--------) & LiteX (--------) on 2022-02-07 17:23:11
|
||||
//--------------------------------------------------------------------------------
|
||||
#include <generated/soc.h>
|
||||
#ifndef __GENERATED_CSR_H
|
||||
#define __GENERATED_CSR_H
|
||||
#include <stdint.h>
|
||||
#include <system.h>
|
||||
#ifndef CSR_ACCESSORS_DEFINED
|
||||
#include <hw/common.h>
|
||||
#endif /* ! CSR_ACCESSORS_DEFINED */
|
||||
#ifndef CSR_BASE
|
||||
#define CSR_BASE 0x0L
|
||||
#endif
|
||||
|
||||
/* uart */
|
||||
#define CSR_UART_BASE (CSR_BASE + 0x0L)
|
||||
#define CSR_UART_RXTX_ADDR (CSR_BASE + 0x0L)
|
||||
#define CSR_UART_RXTX_SIZE 1
|
||||
static inline uint32_t uart_rxtx_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x0L);
|
||||
}
|
||||
static inline void uart_rxtx_write(uint32_t v) {
|
||||
csr_write_simple(v, CSR_BASE + 0x0L);
|
||||
}
|
||||
#define CSR_UART_TXFULL_ADDR (CSR_BASE + 0x4L)
|
||||
#define CSR_UART_TXFULL_SIZE 1
|
||||
static inline uint32_t uart_txfull_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x4L);
|
||||
}
|
||||
#define CSR_UART_RXEMPTY_ADDR (CSR_BASE + 0x8L)
|
||||
#define CSR_UART_RXEMPTY_SIZE 1
|
||||
static inline uint32_t uart_rxempty_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x8L);
|
||||
}
|
||||
#define CSR_UART_EV_STATUS_ADDR (CSR_BASE + 0xcL)
|
||||
#define CSR_UART_EV_STATUS_SIZE 1
|
||||
static inline uint32_t uart_ev_status_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0xcL);
|
||||
}
|
||||
#define CSR_UART_EV_STATUS_TX_OFFSET 0
|
||||
#define CSR_UART_EV_STATUS_TX_SIZE 1
|
||||
static inline uint32_t uart_ev_status_tx_extract(uint32_t oldword) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return ( (oldword >> 0) & mask );
|
||||
}
|
||||
static inline uint32_t uart_ev_status_tx_read(void) {
|
||||
uint32_t word = uart_ev_status_read();
|
||||
return uart_ev_status_tx_extract(word);
|
||||
}
|
||||
#define CSR_UART_EV_STATUS_RX_OFFSET 1
|
||||
#define CSR_UART_EV_STATUS_RX_SIZE 1
|
||||
static inline uint32_t uart_ev_status_rx_extract(uint32_t oldword) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return ( (oldword >> 1) & mask );
|
||||
}
|
||||
static inline uint32_t uart_ev_status_rx_read(void) {
|
||||
uint32_t word = uart_ev_status_read();
|
||||
return uart_ev_status_rx_extract(word);
|
||||
}
|
||||
#define CSR_UART_EV_PENDING_ADDR (CSR_BASE + 0x10L)
|
||||
#define CSR_UART_EV_PENDING_SIZE 1
|
||||
static inline uint32_t uart_ev_pending_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x10L);
|
||||
}
|
||||
static inline void uart_ev_pending_write(uint32_t v) {
|
||||
csr_write_simple(v, CSR_BASE + 0x10L);
|
||||
}
|
||||
#define CSR_UART_EV_PENDING_TX_OFFSET 0
|
||||
#define CSR_UART_EV_PENDING_TX_SIZE 1
|
||||
static inline uint32_t uart_ev_pending_tx_extract(uint32_t oldword) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return ( (oldword >> 0) & mask );
|
||||
}
|
||||
static inline uint32_t uart_ev_pending_tx_read(void) {
|
||||
uint32_t word = uart_ev_pending_read();
|
||||
return uart_ev_pending_tx_extract(word);
|
||||
}
|
||||
static inline uint32_t uart_ev_pending_tx_replace(uint32_t oldword, uint32_t plain_value) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
|
||||
}
|
||||
static inline void uart_ev_pending_tx_write(uint32_t plain_value) {
|
||||
uint32_t oldword = uart_ev_pending_read();
|
||||
uint32_t newword = uart_ev_pending_tx_replace(oldword, plain_value);
|
||||
uart_ev_pending_write(newword);
|
||||
}
|
||||
#define CSR_UART_EV_PENDING_RX_OFFSET 1
|
||||
#define CSR_UART_EV_PENDING_RX_SIZE 1
|
||||
static inline uint32_t uart_ev_pending_rx_extract(uint32_t oldword) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return ( (oldword >> 1) & mask );
|
||||
}
|
||||
static inline uint32_t uart_ev_pending_rx_read(void) {
|
||||
uint32_t word = uart_ev_pending_read();
|
||||
return uart_ev_pending_rx_extract(word);
|
||||
}
|
||||
static inline uint32_t uart_ev_pending_rx_replace(uint32_t oldword, uint32_t plain_value) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
|
||||
}
|
||||
static inline void uart_ev_pending_rx_write(uint32_t plain_value) {
|
||||
uint32_t oldword = uart_ev_pending_read();
|
||||
uint32_t newword = uart_ev_pending_rx_replace(oldword, plain_value);
|
||||
uart_ev_pending_write(newword);
|
||||
}
|
||||
#define CSR_UART_EV_ENABLE_ADDR (CSR_BASE + 0x14L)
|
||||
#define CSR_UART_EV_ENABLE_SIZE 1
|
||||
static inline uint32_t uart_ev_enable_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x14L);
|
||||
}
|
||||
static inline void uart_ev_enable_write(uint32_t v) {
|
||||
csr_write_simple(v, CSR_BASE + 0x14L);
|
||||
}
|
||||
#define CSR_UART_EV_ENABLE_TX_OFFSET 0
|
||||
#define CSR_UART_EV_ENABLE_TX_SIZE 1
|
||||
static inline uint32_t uart_ev_enable_tx_extract(uint32_t oldword) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return ( (oldword >> 0) & mask );
|
||||
}
|
||||
static inline uint32_t uart_ev_enable_tx_read(void) {
|
||||
uint32_t word = uart_ev_enable_read();
|
||||
return uart_ev_enable_tx_extract(word);
|
||||
}
|
||||
static inline uint32_t uart_ev_enable_tx_replace(uint32_t oldword, uint32_t plain_value) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
|
||||
}
|
||||
static inline void uart_ev_enable_tx_write(uint32_t plain_value) {
|
||||
uint32_t oldword = uart_ev_enable_read();
|
||||
uint32_t newword = uart_ev_enable_tx_replace(oldword, plain_value);
|
||||
uart_ev_enable_write(newword);
|
||||
}
|
||||
#define CSR_UART_EV_ENABLE_RX_OFFSET 1
|
||||
#define CSR_UART_EV_ENABLE_RX_SIZE 1
|
||||
static inline uint32_t uart_ev_enable_rx_extract(uint32_t oldword) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return ( (oldword >> 1) & mask );
|
||||
}
|
||||
static inline uint32_t uart_ev_enable_rx_read(void) {
|
||||
uint32_t word = uart_ev_enable_read();
|
||||
return uart_ev_enable_rx_extract(word);
|
||||
}
|
||||
static inline uint32_t uart_ev_enable_rx_replace(uint32_t oldword, uint32_t plain_value) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
|
||||
}
|
||||
static inline void uart_ev_enable_rx_write(uint32_t plain_value) {
|
||||
uint32_t oldword = uart_ev_enable_read();
|
||||
uint32_t newword = uart_ev_enable_rx_replace(oldword, plain_value);
|
||||
uart_ev_enable_write(newword);
|
||||
}
|
||||
#define CSR_UART_TUNING_WORD_ADDR (CSR_BASE + 0x18L)
|
||||
#define CSR_UART_TUNING_WORD_SIZE 1
|
||||
static inline uint32_t uart_tuning_word_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x18L);
|
||||
}
|
||||
static inline void uart_tuning_word_write(uint32_t v) {
|
||||
csr_write_simple(v, CSR_BASE + 0x18L);
|
||||
}
|
||||
#define CSR_UART_CONFIGURED_ADDR (CSR_BASE + 0x1cL)
|
||||
#define CSR_UART_CONFIGURED_SIZE 1
|
||||
static inline uint32_t uart_configured_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x1cL);
|
||||
}
|
||||
static inline void uart_configured_write(uint32_t v) {
|
||||
csr_write_simple(v, CSR_BASE + 0x1cL);
|
||||
}
|
||||
|
||||
/* ctrl */
|
||||
#define CSR_CTRL_BASE (CSR_BASE + 0x800L)
|
||||
#define CSR_CTRL_RESET_ADDR (CSR_BASE + 0x800L)
|
||||
#define CSR_CTRL_RESET_SIZE 1
|
||||
static inline uint32_t ctrl_reset_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x800L);
|
||||
}
|
||||
static inline void ctrl_reset_write(uint32_t v) {
|
||||
csr_write_simple(v, CSR_BASE + 0x800L);
|
||||
}
|
||||
#define CSR_CTRL_RESET_SOC_RST_OFFSET 0
|
||||
#define CSR_CTRL_RESET_SOC_RST_SIZE 1
|
||||
static inline uint32_t ctrl_reset_soc_rst_extract(uint32_t oldword) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return ( (oldword >> 0) & mask );
|
||||
}
|
||||
static inline uint32_t ctrl_reset_soc_rst_read(void) {
|
||||
uint32_t word = ctrl_reset_read();
|
||||
return ctrl_reset_soc_rst_extract(word);
|
||||
}
|
||||
static inline uint32_t ctrl_reset_soc_rst_replace(uint32_t oldword, uint32_t plain_value) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
|
||||
}
|
||||
static inline void ctrl_reset_soc_rst_write(uint32_t plain_value) {
|
||||
uint32_t oldword = ctrl_reset_read();
|
||||
uint32_t newword = ctrl_reset_soc_rst_replace(oldword, plain_value);
|
||||
ctrl_reset_write(newword);
|
||||
}
|
||||
#define CSR_CTRL_RESET_CPU_RST_OFFSET 1
|
||||
#define CSR_CTRL_RESET_CPU_RST_SIZE 1
|
||||
static inline uint32_t ctrl_reset_cpu_rst_extract(uint32_t oldword) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return ( (oldword >> 1) & mask );
|
||||
}
|
||||
static inline uint32_t ctrl_reset_cpu_rst_read(void) {
|
||||
uint32_t word = ctrl_reset_read();
|
||||
return ctrl_reset_cpu_rst_extract(word);
|
||||
}
|
||||
static inline uint32_t ctrl_reset_cpu_rst_replace(uint32_t oldword, uint32_t plain_value) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
|
||||
}
|
||||
static inline void ctrl_reset_cpu_rst_write(uint32_t plain_value) {
|
||||
uint32_t oldword = ctrl_reset_read();
|
||||
uint32_t newword = ctrl_reset_cpu_rst_replace(oldword, plain_value);
|
||||
ctrl_reset_write(newword);
|
||||
}
|
||||
#define CSR_CTRL_SCRATCH_ADDR (CSR_BASE + 0x804L)
|
||||
#define CSR_CTRL_SCRATCH_SIZE 1
|
||||
static inline uint32_t ctrl_scratch_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x804L);
|
||||
}
|
||||
static inline void ctrl_scratch_write(uint32_t v) {
|
||||
csr_write_simple(v, CSR_BASE + 0x804L);
|
||||
}
|
||||
#define CSR_CTRL_BUS_ERRORS_ADDR (CSR_BASE + 0x808L)
|
||||
#define CSR_CTRL_BUS_ERRORS_SIZE 1
|
||||
static inline uint32_t ctrl_bus_errors_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x808L);
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,9 @@
|
||||
//--------------------------------------------------------------------------------
|
||||
// Auto-generated by Migen (--------) & LiteX (--------) on 2022-02-07 17:23:11
|
||||
//--------------------------------------------------------------------------------
|
||||
#ifndef __GENERATED_GIT_H
|
||||
#define __GENERATED_GIT_H
|
||||
|
||||
#define MIGEN_GIT_SHA1 "--------"
|
||||
#define LITEX_GIT_SHA1 "--------"
|
||||
#endif
|
||||
@ -0,0 +1,15 @@
|
||||
//--------------------------------------------------------------------------------
|
||||
// Auto-generated by Migen (--------) & LiteX (--------) on 2022-02-07 17:23:11
|
||||
//--------------------------------------------------------------------------------
|
||||
#ifndef __GENERATED_MEM_H
|
||||
#define __GENERATED_MEM_H
|
||||
|
||||
#ifndef CSR_BASE
|
||||
#define CSR_BASE 0x00000000L
|
||||
#define CSR_SIZE 0x00010000
|
||||
#endif
|
||||
|
||||
#ifndef MEM_REGIONS
|
||||
#define MEM_REGIONS "CSR 0x00000000 0x10000 "
|
||||
#endif
|
||||
#endif
|
||||
@ -0,0 +1,40 @@
|
||||
//--------------------------------------------------------------------------------
|
||||
// Auto-generated by Migen (--------) & LiteX (--------) on 2022-02-07 17:23:11
|
||||
//--------------------------------------------------------------------------------
|
||||
#ifndef __GENERATED_SOC_H
|
||||
#define __GENERATED_SOC_H
|
||||
#define CONFIG_CLOCK_FREQUENCY 48000000
|
||||
#define CONFIG_CPU_TYPE_NONE
|
||||
#define CONFIG_CPU_VARIANT_STANDARD
|
||||
#define CONFIG_CPU_HUMAN_NAME "Unknown"
|
||||
#define CONFIG_CSR_DATA_WIDTH 32
|
||||
#define CONFIG_CSR_ALIGNMENT 32
|
||||
#define CONFIG_BUS_STANDARD "WISHBONE"
|
||||
#define CONFIG_BUS_DATA_WIDTH 32
|
||||
#define CONFIG_BUS_ADDRESS_WIDTH 32
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
static inline int config_clock_frequency_read(void) {
|
||||
return 48000000;
|
||||
}
|
||||
static inline const char * config_cpu_human_name_read(void) {
|
||||
return "Unknown";
|
||||
}
|
||||
static inline int config_csr_data_width_read(void) {
|
||||
return 32;
|
||||
}
|
||||
static inline int config_csr_alignment_read(void) {
|
||||
return 32;
|
||||
}
|
||||
static inline const char * config_bus_standard_read(void) {
|
||||
return "WISHBONE";
|
||||
}
|
||||
static inline int config_bus_data_width_read(void) {
|
||||
return 32;
|
||||
}
|
||||
static inline int config_bus_address_width_read(void) {
|
||||
return 32;
|
||||
}
|
||||
#endif // !__ASSEMBLER__
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue