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6 lines
315 B
Plaintext
6 lines
315 B
Plaintext
verilog_defaults -push
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verilog_defaults -add -defer
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read_verilog /home/matt/3rd/fpga/microwatt/valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.v
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verilog_defaults -pop
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attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0
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synth_ecp5 -json valentyusb.json -top valentyusb |