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1.3 KiB
1.3 KiB
A2 Interfaces to WB
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core interfaces
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A2I/A2O A2L2 bus
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Single (combined I/D) w/SMP extensions
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Dual (separate I/D) WB buses w/SMP extensions
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bus interfaces
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single WB
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dual WB
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functions
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queues one or more core commands
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point of coherncy for larx/stcx, sync, tlbie, etc. for multicores below it (single/mulithread)
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address compares necessary for ordering/coherency
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optional mailbox interface for core-core peer and broadcast
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arbitrates for WB bus(es)
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gen responses for cores
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Possible configurations
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one core, WB: pass-through with SMP functions
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one core, A2L2: bridge with SMP functions
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multi-core: identical or mixed WB1/WB2/A2L2, queueing, arbitration, and SMP functions
syntax check
verilator --lint-only a2wb.v -Wno-LITENDIAN
sim build
verilator --cc --exe --trace -Wno-Litendian -Wno-fatal -I./src top.v tb.cpp
cd obj_dir;make -f Vtop.mk;cd ..
obj_dir/Vtop
synth build (Litex)
- had to make some source changes for Vivado
rm obj_dir/*
# use sim top so tb.cpp is ok
verilator --cc --exe --trace -Wno-Litendian -Wno-fatal -I./litex/a2node/verilog -I./src top.v tb.cpp uart.cpp
cd obj_dir;make -f Vtop.mk;cd ..
obj_dir/Vtop
gtkwave wtf.vcd wtf.gtkw
vcd2fst wtf.vcd wtf.fst
gtkwave wtf.fst wtf.gtkw